Self-Aligned Backside Contact Structure for Overlay Margin
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Solution Overview
Problem
The challenge of forming a self-aligned backside contact in semiconductor devices to mitigate poor overlay margin at the wafer backside is unresolved in existing technologies, requiring placeholder formation and selective backside silicon removal.
Innovation Solution
A method involving the formation of additional and sacrificial semiconductor layers, replacement with an etch stop layer, indentation to create a space for an inner spacer, and formation of a self-aligned backside contact insulated by the etch stop layer, along with backside trench S/D epitaxy to improve alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If placeholder formation and selective backside silicon removal are used, then self-aligned backside contact can be achieved, but the process complexity increases and overlay margin issues persist
Solution Approach 1:
The patent forms the backside contact structure during the frontside processing stage, before wafer backside access is needed. The contact plug is created through the substrate thickness while the frontside gate and source/drain structures are being formed, eliminating the need for separate placeholder formation and backside silicon removal steps.
Solution Approach 2:
The patent combines the formation of the backside contact with the frontside device fabrication process. The contact plug formation, insulation layer deposition, and patterning are integrated into the existing frontside process sequence, eliminating the need for separate backside processing steps.
2Manufacturing precision
If additional processing steps are added to achieve self-aligned backside contact, then alignment accuracy improves, but fabrication time increases
Solution Approach 1:
The backside contact plug is formed during frontside processing when the wafer is still accessible from the frontside, utilizing the existing process window and alignment references. This preliminary formation eliminates the need for additional backside alignment steps that would consume extra time.
Solution Approach 2:
The frontside device structures (gate, source/drain) serve as self-aligned references for the backside contact formation. The contact plug automatically aligns to these structures through the substrate thickness without requiring separate alignment operations, using the frontside features themselves as the alignment reference.
3Ease of manufacture
If conventional backside contact formation is used, then process simplicity is maintained, but poor overlay margin at wafer backside persists
Solution Approach 1:
The backside contact structure is formed in advance during frontside processing, when precise alignment can be achieved using the frontside device features as references. This preliminary formation ensures good overlay margin before the wafer is flipped for backside access.
Solution Approach 2:
The substrate itself acts as an intermediary, allowing the backside contact plug to be formed through it during frontside processing. The plug extends through the substrate thickness and will later connect to the backside surface, using the substrate as a medium to bridge the frontside and backside structures.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes source/drain (S/D) epitaxy, a gate stack adjacent to the S/D epitaxy, a semiconductor layer underlying the gate stack and including a semiconductor material surrounded by an inner spacer, an etch stop layer underlying the semiconductor layer, back trench S/D epitaxy and a self-aligned backside contact. The backside trench S/D epitaxy contacts the S/D epitaxy and is insulated from the semiconductor material by the inner spacer. The self-aligned backside contact contacts the backside trench S/D epitaxy and is insulated from the semiconductor material by the etch stop layer.