Backside Contact Pillar Patterning for Void-Free Power Rails
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Solution Overview
Problem
As semiconductor node sizes shrink, the congestion in signal and power line space in the back-end-of-line (BEOL) region increases, necessitating the movement of power lines to a backside power distribution network (BSPDN) below the front-end-of-line (FEOL) layers, requiring new forms of contacts between backside power rails and device terminals to ensure accurate alignment and prevent misalignments and voids that can cause circuit malfunctions.
Innovation Solution
A semiconductor unit with a backside contact in the substrate, having a positive slope and lined with a dielectric liner, which connects semiconductor device terminals to backside power rails, ensuring precise alignment and preventing misalignments and voids by using a self-aligned etching process or forming a dielectric liner on the sidewalls of the backside contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power lines are moved to a backside power distribution network below the FEOL layers, then congestion in signal and power line space in the BEOL region is reduced, but misalignment and voids in backside contacts occur causing circuit malfunctions
Solution Approach 1:
A pillar structure is formed in the substrate before the semiconductor device is constructed. This preliminary structure serves as a template that guides subsequent processing steps, ensuring that backside contacts are accurately positioned relative to device terminals from the outset, preventing misalignment issues.
Solution Approach 2:
The pillar structure acts as an intermediary element between the substrate and the final backside contact. It provides a mechanical and positional reference that mediates the alignment between the power distribution network and device terminals, eliminating direct alignment challenges.
2Ease of manufacture
If conventional contact formation methods are used for backside contacts, then manufacturing simplicity is maintained, but misalignments and voids occur causing device failure
Solution Approach 1:
The pillar structure is created during substrate preparation, before device fabrication. This preliminary action establishes precise positional references that simplify subsequent contact formation steps while ensuring high alignment precision, as the pillar automatically defines the contact location.
Solution Approach 2:
The pillar structure is self-aligned to the device terminals through the fabrication process. The same process steps that define device geometry also define pillar geometry, making the pillar self-positioned without requiring additional alignment operations, thus achieving both simplicity and precision.
Data Source
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AI summary
In order to achieve higher contact quality for backside power distribution networks, provided is a backside contact to a semiconductor device having a positive slope and a dielectric sidewall liner, and methods for making the same.