Backside Contact Plug Structure for Low-RC Semiconductor Power Rails
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down semiconductor devices due to limitations in backend of lines (BEOL) metal layers, including increased resistance and capacitance, which affect device performance and complexity, particularly in integrating gate-all-around (GAA) transistors with complex backside power rail architectures.
Innovation Solution
A semiconductor structure with a backside power rail architecture is introduced, featuring a sacrificial layer in source/drain recesses and self-aligned backside contact plugs, reducing parasitic capacitance and improving RC delay and IR voltage drop by using a wider lower portion connected to the backside metal line, while maintaining a narrower upper portion aligned with the source/drain features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BEOL metal layers are used in scaled-down semiconductor devices, then manufacturing process is simpler, but resistance and capacitance increase affecting device performance
Solution Approach 1:
The patent introduces a backside power rail architecture that routes power and ground metals on the backside of the substrate, utilizing the third dimension (vertical stacking) to separate power routing from signal routing. This dimensional separation reduces parasitic effects and improves performance without increasing lateral complexity.
Solution Approach 2:
The patent uses intermediate structures such as contact plugs, vias, and isolation layers to mediate between the frontside circuitry and backside power rails. These intermediary elements enable efficient power delivery while managing the complexity of interconnections between different metal layers.
2Reliability
If gate-all-around transistor structures are integrated, then gate control and short-channel effects are improved, but fabrication complexity increases
Solution Approach 1:
The patent employs preliminary actions by forming sacrificial layers and using self-aligned processes before final gate structure formation. These preliminary steps establish precise geometric constraints that guide subsequent fabrication steps, enabling complex GAA structures to be manufactured with conventional process tools.
Solution Approach 2:
The gate-all-around structure inherently nests the gate electrode within the channel region, providing 360-degree control. The patent extends this nesting principle to the power rail architecture, where backside power rails are nested beneath the substrate, creating a compact integrated structure that improves gate control without proportionally increasing fabrication complexity.
3Speed
If metal conductor width is increased to reduce resistance, then RC delay improves, but area and device complexity increase
Solution Approach 1:
The backside power rail architecture utilizes the vertical dimension to create wide, low-resistance power paths beneath the substrate without consuming lateral area. By routing power metals in the vertical stack rather than laterally across the chip, the design achieves low RC delay while maintaining compact device footprint.
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes forming an active region over a substrate, etching the active region to form a recess, forming a sacrificial layer in the recess, forming a source/drain feature over the sacrificial layer in the recess, removing the substrate, etching the active region and the sacrificial layer to form an opening exposing a backside surface of the source/drain feature, and forming a first contact plug in the opening.