Backside Contact Isolation for Low-Resistance Semiconductor Power Rails
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Solution Overview
Problem
As integrated circuits (IC) scale down, the power rails become thinner, leading to increased voltage drop and power consumption. Moving some power rails to the backside of transistors is desirable, but it poses a challenge in isolating these backside power rails from transistor components like metal gates.
Innovation Solution
The solution involves forming backside power rails and vias in semiconductor devices, while isolating them from nearby conductors such as metal gates using an isolating layer. This approach increases the number of metal tracks for direct connection to source/drain contacts and enhances gate density for greater device integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power rails are moved to the backside of transistors, then power rail resistance is reduced due to wider dimensions, but isolation from transistor components such as metal gates becomes more difficult
Solution Approach 1:
An isolating layer is introduced as an intermediary between the backside power rails and transistor components such as metal gates. This isolating layer acts as a mediator that prevents direct electrical interaction while allowing the backside power rails to maintain their low-resistance configuration. The isolating layer is specifically positioned to separate conductors that would otherwise be in close proximity due to the backside contact architecture.
Solution Approach 2:
The device structure is segmented into distinct regions with different functions: the backside contains power rails optimized for low resistance, while the front side contains transistor components. The isolating layer creates clear segmentation between these regions, allowing each to be optimized independently. This segmentation enables the backside power rails to achieve wider dimensions and lower resistance without compromising the integrity of the transistor components.
2Volume of moving object
If integrated circuits are scaled down, then device size is reduced, but voltage drop across power rails increases
Solution Approach 1:
The power rail configuration transitions from a planar (2D) layout to a three-dimensional (3D) stacked architecture. By moving power rails to the backside and utilizing vertical stacking, the effective cross-sectional area of power delivery paths is increased without increasing the planar footprint. This dimensional transition allows wider power rail dimensions to be achieved in the vertical dimension, thereby reducing resistance and voltage drop while maintaining scaled-down device size.
Solution Approach 2:
Power delivery functions are merged across multiple layers and dimensions. The backside power rails are combined with frontside interconnect structures through vertical alignment and electrical connection, creating a hybrid power delivery system. This merging allows the device to leverage both the wide, low-resistance backside rails and the compact frontside interconnect architecture, achieving low voltage drop in a scaled device.
Data Source
AI summary
A semiconductor structure includes an isolation structure, a source/drain region over the isolation structure, a gate structure over the isolation structure and adjacent to the source/drain region, an interconnect layer over the source/drain region and the gate structure, an isolating layer below the gate structure, and a contact structure under the source/drain region. The contact structure has a first portion and a second portion. The first portion is below the second portion. The second portion extends through the isolating layer and protrudes above the isolating layer. A portion of the isolating layer is vertically between the gate structure and the first portion of the contact structure.