Backside Contact Rail Layout for Low-Drop GAA Power Delivery

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Solution Overview

Problem

Existing integrated circuit designs face challenges in efficiently providing power to header cells through power rails, particularly in gate-all-around transistors, leading to inefficiencies and potential voltage drops.

Innovation Solution

The formation of backside power rails and contact rails in gate-all-around transistors, utilizing CMG regions and via rails to connect to ungated and gated power supplies, enabling efficient power distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If power is provided through conventional power rails in header cells, then power distribution is achieved, but voltage drops occur and power delivery efficiency is reduced

Engineering Contradiction:
Improvevoltage dropVSAvoidpower delivery efficiency
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent introduces contact rails extending in a first direction (perpendicular to gate stacks) and via rails extending in a second direction (along gate stacks), creating a three-dimensional power distribution network. This multi-directional rail structure transforms the conventional two-dimensional power rail approach, enabling power to reach header cells through multiple spatial paths and reducing voltage drops by distributing current across different dimensional routes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If conventional power rails are used in gate-all-around transistors, then power supply is provided, but inefficiencies and voltage drops occur

Engineering Contradiction:
Improvepower delivery efficiencyVSAvoidvoltage drop
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The power distribution network is segmented into distinct functional components: contact rails for horizontal power distribution, via rails for vertical power distribution, and header cells for power switching. This segmentation allows each component to be optimized for its specific function, with contact rails minimizing horizontal resistance and via rails providing vertical power delivery, thereby improving overall power delivery efficiency while reducing voltage drops.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a three-dimensional power distribution architecture where contact rails extend perpendicular to gate stacks and via rails extend parallel to gate stacks, creating orthogonal power delivery paths. This multi-dimensional approach enables power to reach header cells through multiple spatial routes, reducing current density in any single path and minimizing voltage drops.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If backside power rails and contact rails are formed using CMG regions and via rails, then power distribution efficiency is improved, but device structure complexity increases

Engineering Contradiction:
Improvepower distribution efficiencyVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The contact rails and via rails serve multiple functions: they provide power distribution pathways, act as structural support elements, and enable both horizontal and vertical power delivery. This multi-functionality reduces the need for separate dedicated structures, thereby improving power distribution efficiency while limiting the increase in overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12507438B2Semiconductor structure with contact rail and method for forming the same
Publication Date: 2025.12.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12507438B2 patent drawing
  • US12507438B2 patent drawing
  • US12507438B2 patent drawing

AI summary

A method includes forming a gate electrode and a source/drain region over a bulk portion of a semiconductor substrate, forming a cut-metal-gate region to separate the gate electrode into a first portion and a second portion, forming a source/drain contact plug overlapping and electrically connected to the source/drain region, forming a first contact rail overlapping a portion of the cut-metal-gate region, removing the bulk portion of the semiconductor substrate, and etching the cut-metal-gate region to form a trench. A surface of the first contact rail is revealed to the trench. A via rail is formed in the trench, and the via rail is electrically connected to the source/drain region through the first contact rail.