Backside Source-Drain Contact Reveal Uniformity in Nanosheet ICs
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, leading to difficulties in achieving uniformity in backside contact reveal and increased risk of front-side to backside shorts, which hinders further miniaturization beyond the 10 nanometer node.
Innovation Solution
The implementation of selective dielectric etches to improve backside contact reveal uniformity and prevent shorts, involving an etch-back of dielectric materials followed by filling with a material that can be polished simultaneously with shallow trench isolation, and the use of angled directional etches for wider via landing areas to enhance contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling multi-gate transistors, then manufacturing simplicity is maintained, but backside contact reveal uniformity deteriorates and front-side to backside shorts increase
Solution Approach 1:
The fabrication process is divided into distinct stages: forming dielectric structures with first dielectric material in trenches, adding second dielectric material, performing selective etch-back to expose contact regions, and filling with conductive material. This segmentation allows precise control over backside contact reveal uniformity while managing process complexity through systematic breakdown of steps.
Solution Approach 2:
Dielectric structures are formed in advance before transistor fabrication is complete. The dielectric materials are deposited and patterned preliminarily, then selectively removed via etch-back to create contact regions. This preliminary action enables controlled reveal of backside contacts while preventing shorts, as the dielectric framework is established before final device completion.
2Productivity
If feature size is reduced to increase device density, then capacity increases, but variability in fabrication processes worsens and uniformity control becomes more difficult
Solution Approach 1:
Different dielectric materials with distinct etch selectivities are used in different spatial regions and for different purposes. The first dielectric material fills trenches and provides structural support, while the second dielectric material fills remaining spaces. Selective etch-back removes specific dielectric layers to expose contact regions with precise dimensional control, achieving uniform backside contact reveal despite scaled dimensions.
Solution Approach 2:
The process utilizes changes in material properties, specifically etch selectivity between different dielectric materials. By selecting dielectric materials with contrasting etch rates and using controlled etch-back parameters, the process achieves precise reveal of backside contacts at scaled dimensions. The conductive material filling step further refines contact dimensions through controlled deposition parameters.
3Manufacturing precision
If selective dielectric etch-back is performed to improve contact reveal uniformity, then backside contact uniformity improves, but process steps and complexity increase
Solution Approach 1:
The dielectric structures serve multiple functions: they provide structural support during fabrication, define contact regions through selective removal, and protect underlying structures during etch-back. The process is self-aligning, where the dielectric framework automatically defines contact locations and dimensions, reducing the need for additional alignment steps and minimizing overall process complexity despite the added etch-back step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures improved uniformity in backside contact reveal, reduces front-side to backside shorts, and allows for reduced power network resistance and cell height, enabling more efficient power delivery and performance enhancements in semiconductor devices.
Implementation Method 1
performing a first etch to remove a portion of the first dielectric material and expose a first contact region
Implementation Method 2
forming a second dielectric material in the trenches and over the first dielectric material
Implementation Method 3
improve backside contact reveal uniformity
Data Source
AI summary
Integrated circuit structures having backside contact reveal uniformity, and methods of fabricating integrated circuit structures having backside contact reveal uniformity, are described. In an example, an integrated circuit structure includes an integrated circuit structure including a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. A conductive source or drain contact is vertically beneath and in contact with a bottom of the epitaxial source or drain structure. The conductive source or drain contact is in a cavity in the isolation layer. The isolation layer extends laterally beneath the gate stack.