Backside Contact Extension Layout for Scaled Nanowire Transistors
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits, particularly at the 10 nanometer node and below, is hindered by variability in conventional fabrication processes, leading to challenges in further reducing feature sizes and increasing device densities.
Innovation Solution
The implementation of backside contact extensions and differentiated access features, including backside power delivery and self-aligned access structures, to enhance contact performance and reduce edge placement errors, while allowing for more efficient integration of nanowires and fins in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling multi-gate transistors, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to variability at 10 nanometer node and below
Solution Approach 1:
The fabrication process is divided into separate front-side and back-side operations. The backside contact extensions are formed independently on the backside of the substrate, then the substrate is flipped to continue front-side processing. This segmentation allows specialized processes for each side, improving precision without overwhelming overall process complexity.
Solution Approach 2:
The patent introduces a third dimension by extending contacts through the substrate thickness from the backside to the frontside. This vertical extension through the substrate enables precise contact formation at specific depths, improving manufacturing precision at nanometer nodes by adding a depth control dimension to the traditional planar fabrication process.
2Quantity of substance
If feature sizes are reduced to increase device densities, then capacity increases, but manufacturing precision deteriorates due to process variability
Solution Approach 1:
By separating contact formation into backside and frontside operations, each side can be optimized independently. The backside contact extensions are formed with controlled dimensions before substrate flipping, allowing precise feature size control even as overall device density increases through further scaling.
Solution Approach 2:
The backside contact extensions are formed in advance before the substrate is flipped for frontside processing. This preliminary action establishes precise contact features early in the process, ensuring controlled dimensions are maintained even as subsequent frontside scaling increases device density.
3Reliability
If backside contact extensions are implemented, then contact performance improves, but device complexity increases
Solution Approach 1:
Instead of forming contacts only from the frontside, the patent inverts the approach by forming contact extensions from the backside of the substrate. These extensions grow upward through the substrate thickness to meet frontside features, improving contact performance through better electrical connection while the inversion symmetry simplifies the overall structural complexity.
Solution Approach 2:
The backside contact extensions serve multiple functions: they provide electrical contact pathways, enable backside power delivery, and facilitate self-aligned access structures. This multi-functionality improves contact performance while reducing the need for separate structures, thereby managing overall device complexity.
4Ease of operation
If substrate flipping is performed for backside access, then contact access improves, but manufacturing complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct front-side and back-side phases separated by a substrate flip. This segmentation provides clear access to each side for specialized operations, improving contact access by allowing independent optimization of each side's processing while managing overall complexity through structured phase separation.
Data Source
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AI summary
Integrated circuit structures having backside contact extensions are described. In an example, a structure includes a first and second pluralities of horizontally stacked nanowires or fins. First and second gate stacks are over the first and second pluralities of horizontally stacked nanowires or fins. An epitaxial source or drain structure is between the first and second pluralities of horizontally stacked nanowires or fin. A dielectric structure is over the first gate stack, over the second gate stack, and over the epitaxial source or drain structure, the dielectric structure having an opening over the epitaxial source or drain. A conductive structure is in the opening in the dielectric structure and on the epitaxial source or drain structure, the conductive structure having a top surface below a top of the opening. A conductive extension is on the conductive structure, the conductive extension in and protruding above the opening in the dielectric structure.