Backside Source-Drain Contact Reveal Using Selective Dielectric Etch
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, leading to difficulties in achieving uniformity in backside contact reveal and increased risk of front-side to backside shorts, which hinders further miniaturization beyond the 10 nanometer node.
Innovation Solution
The implementation of selective dielectric etches to improve backside contact reveal uniformity and prevent shorts, involving an etch-back of dielectric materials selective to shallow trench isolation followed by filling with a material that can be polished simultaneously, along with angled directional etching for wider via landing areas and backside power delivery to reduce power network resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling multi-gate transistors, then manufacturing cost and compatibility with existing infrastructure are maintained, but manufacturing precision and reliability deteriorate due to variability in backside contact reveal
Solution Approach 1:
The fabrication process is divided into distinct segments: front-side processing, backside thinning and contact reveal, and intermediate layer formation. Each segment is optimized independently, with the backside reveal process specifically tailored to achieve uniform contact formation without affecting front-side device performance.
Solution Approach 2:
The backside contact placeholders are formed in advance during front-side processing, and the intermediate dielectric layer is deposited before backside thinning. This preliminary action ensures that contact alignment and uniformity are established before the critical backside reveal step, reducing variability.
2Length of moving object
If feature size is reduced to extend scaling beyond 10 nanometer node, then device density is improved, but manufacturing precision deteriorates due to process variability
Solution Approach 1:
The patent transitions from conventional front-side-only contact formation to backside contact formation, adding a new dimensional approach to the fabrication process. This allows contact alignment to be controlled from the backside, independent of front-side feature scaling, thereby maintaining manufacturing precision at smaller dimensions.
Solution Approach 2:
The process utilizes controlled changes in dielectric layer thickness and etch parameters to maintain uniform contact reveal across scaled features. By adjusting these parameters independently of feature size, the patent achieves consistent manufacturing precision regardless of the nanometer node.
3Reliability
If backside contact reveal is performed without selective etching, then process simplicity is maintained, but reliability deteriorates due to front-side to backside shorts
Solution Approach 1:
Selective dielectric etching is applied locally at the contact placeholder regions rather than uniformly across the entire wafer. This localized approach prevents front-side to backside shorts by selectively removing dielectric material only where contacts are needed, while maintaining process simplicity through targeted treatment of specific areas.
Solution Approach 2:
An intermediate dielectric layer is introduced between the front-side devices and the backside contact structures. This intermediary layer acts as a protective barrier that prevents shorts while allowing controlled removal at contact points, thereby enhancing reliability without significantly complicating the overall manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances backside contact reveal uniformity, prevents front-side to backside shorts, and reduces power network resistance, enabling more efficient and reliable fabrication of integrated circuit structures for future technology nodes.
Implementation Method 1
selective dielectric etches to improve backside contact reveal uniformity and prevent shorts, involving an etch-back of dielectric materials selective to shallow trench isolation
Implementation Method 2
filling with a material that can be polished simultaneously
Implementation Method 3
angled directional etching for wider via landing areas
Data Source
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AI summary
Integrated circuit structures having backside contact reveal uniformity, and methods of fabricating integrated circuit structures having backside contact reveal uniformity, are described. In an example, an integrated circuit structure includes an integrated circuit structure including a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. A conductive source or drain contact is vertically beneath and in contact with a bottom of the epitaxial source or drain structure. The conductive source or drain contact is in a cavity in the isolation layer. The isolation layer extends laterally beneath the gate stack.