Back-Side Contact Arrays Using Self-Assembly Gate Alignment
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Solution Overview
Problem
The formation of back-side contacts and gate vias in integrated circuits is limited by edge placement errors and wafer distortions, leading to misalignments that degrade device performance and hinder further down-scaling of transistor arrays.
Innovation Solution
Utilizing directed self-assembly of sacrificial materials to align back-side contacts and dielectric structures with transistor gate electrodes, enabling precise alignment through the use of self-aligned features and unconventional gate electrode thicknesses to facilitate back-side reveal and subsequent alignment processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning methods are used for back-side contacts, then manufacturing process is simple, but alignment precision between back-side patterns and front-side features degrades due to edge placement errors and wafer distortions
Solution Approach 1:
The patent applies preliminary action by forming sacrificial materials on the front side of the substrate before back-side patterning. These sacrificial materials serve as alignment references that guide subsequent back-side contact formation, ensuring precise alignment between front-side gate electrodes and back-side contacts while eliminating the need for complex real-time alignment procedures
Solution Approach 2:
The patent uses sacrificial materials as intermediary structures that mediate the alignment between front-side and back-side features. These intermediaries are formed on the front side, patterned with precise features, and then used as templates to guide back-side contact formation, effectively transferring alignment information across the substrate thickness without requiring direct alignment between distant features
2Manufacturing precision
If edge placement error compensation is implemented, then alignment precision improves, but manufacturing time and process complexity increase
Solution Approach 1:
The patent performs alignment reference creation in advance during front-side processing. By forming sacrificial materials with precise patterns before back-side contact formation, the alignment references are established beforehand, eliminating the need for time-consuming alignment measurements and adjustments during back-side processing
Solution Approach 2:
The sacrificial materials serve a dual function: they act as both structural elements for the device and as self-aligning references for back-side patterning. This self-service approach allows the structure itself to provide alignment information, eliminating the need for separate alignment reference structures or complex alignment procedures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Achieves near-perfect alignment between front- and back-side features, allowing for continued device scaling and improved IC performance by reducing misalignment errors and enhancing processing precision.
Implementation Method 1
Utilizing directed self-assembly of sacrificial materials to align back-side contacts and dielectric structures with transistor gate electrodes
Data Source
AI summary
Transistor structures between and coupled to front- and back-side interconnect layers may have precisely aligned arrays of contacts and dielectric structures over and under the transistor structures. Transistor structures may have a gate electrode thickness under a channel region one-and-a-half or two times greater than a thickness between adjacent nanoribbons in the channel region. Front- and back-side spacer layers with a same composition may have a discernible interface. Contacts and dielectric structures on a back side may be formed using directed self-assembly of sacrificial materials aligned to gate electrodes revealed on a substrate back side.