Backside Contact Silicide Formation Before BEOL Heat Limits
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Solution Overview
Problem
Existing semiconductor devices face limitations in forming high-quality silicide layers on backside contact structures due to the risk of melting the back-end-of-line (BEOL) structure at high temperatures required for optimal silicidation.
Innovation Solution
Forming a silicide layer on a metal placeholder structure in a front-end-of-line (FEOL) process at temperatures of 900°C or above, allowing for the creation of high-quality silicide layers without damaging the BEOL structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a silicide layer is formed on a backside contact structure at high temperatures (900°C or above), then the quality of the silicide layer and connection performance are improved, but the BEOL structure may melt or be damaged
Solution Approach 1:
The fabrication process is divided into two distinct stages: FEOL process where the silicide layer is formed on the backside contact structure at high temperatures, and BEOL process where the backend interconnect structure is formed at lower temperatures. This temporal and functional segmentation allows each structure to be processed under its optimal temperature conditions without causing damage to the other.
Solution Approach 2:
The silicide layer is formed on the backside contact structure during the FEOL process, which occurs before the BEOL structure is formed. This preliminary action ensures that the temperature-sensitive silicide layer is already in place and protected when the subsequent BEOL processing occurs at lower temperatures.
2Ease of manufacture
If the silicide layer is formed in the BEOL process, then the BEOL structure can be processed together, but the high temperature required for optimal silicidation will damage the already-formed BEOL structure
Solution Approach 1:
The manufacturing process is segmented into FEOL and BEOL stages, with the silicide formation specifically assigned to the FEOL stage. This segmentation allows the silicide layer to be formed under optimal high-temperature conditions before the temperature-sensitive BEOL structure is introduced, maintaining both process efficiency and structural integrity.
Solution Approach 2:
The silicide layer formation is performed as a preliminary action during the FEOL process, before the BEOL structure is formed. This timing ensures that the silicide layer is already established and will not be exposed to the high temperatures that would damage it during subsequent BEOL processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The FEOL process enables the formation of high-quality silicide layers, improving connection performance and reducing contact resistance, thereby enhancing the overall performance of the semiconductor device.
Implementation Method 1
forming a silicide layer on the placeholder structure; forming a silicide layer on a metal placeholder structure in a front-end-of-line (FEOL) process
Data Source
AI summary
Provided is a semiconductor device including backside contact structure with a silicide layer formed in an FEOL process, and a method of manufacturing the same. The method includes: forming a channel structure on a substrate; forming a placeholder structure in the substrate; forming a silicide layer on the placeholder structure; forming a source/drain region on the silicide layer based on the channel structure; forming a gate structure on the channel structure; and forming a backside contact structure on a bottom surface of the placeholder structure.