Backside Contact Routing for Stacked FET Bottom Source/Drain
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Solution Overview
Problem
Stacked FET semiconductor devices face challenges in routing wiring between the bottom source/drain and signal wiring due to the top layer FET blocking potential paths and the risk of shorting to backside power rails.
Innovation Solution
A semiconductor device design with a shallow backside contact and deep via that provides a conductive path between the back end of line interconnect and the bottom source/drain epitaxial, using a bi-layer dielectric fill and sacrificial materials to create gate cuts and contacts, preventing shorts to the backside power rail.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a backside contact is used for wiring between bottom source/drain and signal wiring, then wiring connectivity is improved, but shorting to backside power rails occurs
Solution Approach 1:
The patent applies local quality by creating a shallow backside contact that is selectively positioned and depth-controlled. The contact is made locally at specific regions where signal wiring is needed, while maintaining different depths in different areas. This allows the contact to reach signal wiring layers without penetrating deep enough to contact power rails, thus providing local connectivity while avoiding harmful shorting.
Solution Approach 2:
The patent introduces a depth dimension control mechanism by forming contacts at different depths (shallow vs. deep contacts). The shallow backside contact operates at a controlled depth that intersects signal wiring layers but stops before reaching power rail layers. This dimensional differentiation in contact depth enables selective connectivity to different wiring layers without interference.
2Productivity
If top layer FET blocks potential path for wiring, then device stacking density is improved, but wiring routing between bottom source/drain and signal wiring becomes difficult
Solution Approach 1:
The patent segments the wiring path into multiple independent routes: shallow backside contacts provide direct lateral connectivity at the bottom layer, while deep vias provide vertical connectivity through intermediate layers. This segmentation allows wiring to bypass the blocked path under the top FET by using alternative routed paths through different structural levels, thus maintaining stacking density while solving routing complexity.
Solution Approach 2:
The patent introduces intermediate structures (shallow backside contacts and deep vias) that act as mediators to establish connectivity. These intermediary elements create new wiring pathways that do not require direct penetration under the top FET, thus maintaining the protective blocking function while enabling indirect connectivity through intermediate connection points.
Data Source
AI summary
Embodiments are disclosed for a semiconductor device and a method for fabrication. The device includes a first gate, having a top FET that is disposed above a bottom FET, and in electrical contact with a top source/drain epitaxial (S/D epi) and a back end of line (BEOL) interconnect. Additionally, the device includes the bottom FET. The bottom FET is in electrical contact with a bottom S/D epi. Further, a shallow backside contact is in electrical contact with the bottom S/D epi. Additionally, the device includes a deep via that is in electrical contact with the BEOL interconnect and the shallow backside contact. The deep via and the shallow backside contact provide a conductive path between the BEOL interconnect and the bottom S/D epi.