Backside Contact Extension in Stacked FETs for Short Isolation
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Solution Overview
Problem
The challenge in semiconductor device fabrication is to form a backside contact that extends beyond the edge of an active region to connect a bottom source/drain region to a frontside interconnect through a deep via, while avoiding short circuits and optimizing power rail distribution.
Innovation Solution
The semiconductor device incorporates a stacked field effect transistor (SFET) structure with a backside contact that extends beyond the active region edge, connected via a deep via. This structure includes multiple stacked transistors, backside power rails, and metallization that passes through and is insulated from the power rails, ensuring proper connection and avoiding short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a backside contact is extended beyond the active region edge to connect bottom S/D region to frontside interconnect, then connection efficiency is improved, but risk of short circuit increases
Solution Approach 1:
The patent introduces an intermediary structure (isolation layer or dielectric material) between the extended backside contact and the active region edge. This mediator prevents direct electrical contact that would cause short circuits while allowing the backside contact to extend beyond the active region for improved connection efficiency to the bottom source/drain region.
Solution Approach 2:
The patent resolves the short circuit risk by transitioning the isolation approach from a planar (2D) configuration to a three-dimensional (3D) structure. The backside contact extends in the vertical dimension beyond the active region edge, with isolation provided in the lateral dimension, creating spatial separation that prevents short circuits while maintaining connection efficiency.
2Power
If multiple stacked transistors are implemented with backside power rails, then power distribution efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements power distribution in the vertical dimension by stacking multiple transistors and placing backside power rails beneath the active region. This 3D configuration allows efficient power delivery to multiple transistor levels without proportionally increasing lateral space requirements, improving power distribution efficiency while managing complexity through vertical integration.
Solution Approach 2:
The backside power rails serve multiple functions: they provide power distribution to stacked transistors, act as a common reference potential, and enable vertical interconnect routing. This multi-functionality improves power distribution efficiency across the stacked device architecture while reducing the need for separate dedicated structures for each function.
3Reliability
If backside contact extends through deep via to connect bottom S/D region, then voltage drop is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary placeholder structures formed during earlier fabrication steps to define the precise location and dimensions of the backside contact and deep via. These placeholders are formed before substrate removal and backside processing, establishing alignment references that guide subsequent steps and reduce the precision burden on later high-risk operations.
Solution Approach 2:
The patent inverts the conventional fabrication sequence by performing backside contact formation and deep via etching after substrate removal, rather than before. This reversed approach allows the use of the frontside placeholder structures as alignment templates for backside processing, improving alignment precision while achieving the low-voltage-drop connection through the deep via.
Data Source
AI summary
A semiconductor device is provided and includes a first transistor including a first source/drain (S/D) region, a second transistor stacked over the first transistor and including a second S/D region, a first backside power rail (BPR) disposed below the first transistor, a second BPR disposed below the first BPR, a via by which the second S/D region and the first BPR are connected and metallization. The metallization passes through and is insulated from the first BPR. The first S/D region and the second BPR are connected by the metallization.