Backside Contact Stitching for Low-Resistance Nanowire Interconnects
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Solution Overview
Problem
Current semiconductor fabrication processes face challenges in scaling to sub-10 nanometer nodes due to variability and constraints on interconnects, particularly in forming long backside power tracks and registering tight-pitch interconnects, which affects the performance and density of integrated circuits.
Innovation Solution
The method involves stitching multiple short backside contact regions to form local interconnects between transistors and interconnect layers, using directed self-assembly to self-align these stitches and reduce contact-to-gate shorts, and implementing backside power delivery to alleviate area and performance issues by eliminating front-side power routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then existing infrastructure compatibility is maintained, but manufacturing precision and reliability deteriorate at sub-10 nanometer nodes
Solution Approach 1:
The fabrication process is divided into separate modules: forming sacrificial nanowire structures, depositing gate materials, removing sacrificial layers, and filling contacts. This segmentation allows each step to be optimized independently for sub-10nm precision while using existing fabrication infrastructure.
Solution Approach 2:
Sacrificial nanowire structures serve as intermediary elements that define the final transistor geometry. These temporary structures enable precise feature formation through self-aligned processes, improving manufacturing precision at sub-10nm nodes while maintaining compatibility with conventional fabrication flows.
2Loss of energy
If front-side power routing is used, then power delivery is achieved, but chip area is consumed and interconnect resistance increases
Solution Approach 1:
Power delivery is moved from the traditional front-side (two-dimensional planar routing) to the backside of the chip, utilizing the third dimension (vertical stacking). This allows power interconnects to run underneath the active circuit area, reducing both power network resistance and the area consumed by power routing.
Solution Approach 2:
The backside contact structures serve dual purposes: they provide mechanical support for the chip and simultaneously function as power delivery interconnects. This merging of structural and electrical functions eliminates the need for separate power routing layers, reducing both area and resistance.
3Productivity
If transistor density is increased, then circuit capacity is improved, but variability in fabrication processes increases
Solution Approach 1:
The sacrificial nanowire structures self-align during deposition, creating automatically aligned gate and contact features. This self-alignment mechanism reduces registration errors and process variability, enabling higher device density without compromising reliability.
Solution Approach 2:
The fabrication process uses material composition changes (different semiconductor materials for sacrificial nanowires vs. final transistor channels) to enable selective removal and formation steps. This parameter control allows precise feature definition at high density while maintaining process reliability through material-based rather than purely geometric control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power network resistance, allows for thinner metal layers, and enhances performance by enabling wider interconnects and reduced interconnect layers, facilitating more efficient power delivery and improved circuit density.
Implementation Method 1
A conductive contact structure is beneath and in contact with the first epitaxial source or drain structure and the second epitaxial source or drain structure. The conductive contact structure is continuous between the first epitaxial source or drain structure and the second epitaxial source or drain structure.
Implementation Method 2
using directed self-assembly to self-align these stitches and reduce contact-to-gate shorts
Data Source
AI summary
Integrated circuit structures having backside contact stitching are described. In an example, an integrated circuit structure includes a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires. First and second epitaxial source or drain structure are at respective ends of the first and second pluralities of horizontally stacked nanowires. A conductive contact structure is beneath and in contact with the first epitaxial source or drain structure and the second epitaxial source or drain structure, and the conductive contact structure is continuous between the first and second epitaxial source or drain structures. The conductive contact structure has a first vertical thickness beneath the first and second epitaxial source or drain structures greater than a second vertical thickness in a region between the first and second epitaxial source or drain structures.