Backside Contact Stitching for Low-Resistance IC Power Delivery
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Solution Overview
Problem
Current semiconductor fabrication processes face challenges in scaling to sub-10 nanometer nodes due to variability and constraints on interconnects, particularly in forming long backside power tracks and integrating backside power delivery without increasing interconnect resistivity and capacitance, while maintaining performance and reducing cell height.
Innovation Solution
The method involves stitching multiple short backside contact regions to form local interconnects between transistors and backside interconnect layers, using directed self-assembly to self-align stitches and metallizing them, allowing for backside power delivery directly from the wafer, reducing power network resistance and enabling free cell placement without power delivery complications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then existing infrastructure compatibility is maintained, but manufacturing precision and reliability deteriorate at sub-10 nanometer nodes
Solution Approach 1:
The patent segments the backside contact formation into multiple discrete contact regions that are individually formed and then stitched together. This segmentation allows each contact region to be precisely controlled at sub-10nm scales while maintaining overall reliability through the stitching interconnect structure that connects these segmented contacts.
Solution Approach 2:
The patent transitions from conventional planar contact formation to a three-dimensional approach by forming contacts on the backside of the substrate and using vertical stitching interconnects to connect these backside contacts to frontside structures. This dimensional change enables precise control of contact dimensions while maintaining substrate integrity.
2Power
If long backside power tracks are formed, then power delivery capability is improved, but interconnect resistivity and capacitance increase
Solution Approach 1:
The patent divides the backside power delivery network into multiple short track segments rather than forming long continuous tracks. Each segment connects adjacent power contacts, and the stitching interconnects provide vertical power pathways. This segmentation reduces the length of each individual interconnect segment, thereby reducing resistive losses while maintaining overall power delivery capability.
Solution Approach 2:
The patent introduces vertical power delivery pathways through stitching interconnects that extend from the backside contact regions through the substrate to frontside interconnect layers. This three-dimensional power delivery architecture reduces the need for long lateral power tracks, thereby reducing interconnect resistivity and capacitance while maintaining power delivery capability.
3Loss of energy
If wide power wires are used for backside power delivery, then power network resistance is reduced, but cell height and interconnect pitch are increased
Solution Approach 1:
The patent transitions from two-dimensional wide power wires to three-dimensional stitching interconnects that provide vertical power pathways. These stitching interconnects reduce power network resistance by providing direct vertical connection paths through the substrate, eliminating the need for wide lateral power wires that would increase cell height.
Solution Approach 2:
The patent segments the power delivery function across multiple vertical stitching interconnects distributed throughout the structure, rather than relying on a few wide horizontal power wires. This segmentation allows power to be delivered through multiple parallel vertical pathways, reducing overall resistance without requiring increased cell height.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power network resistance, improves performance by eliminating the need for wide power wires, and allows for more efficient use of resources, enabling smaller cell height and increased interconnect pitch while maintaining high performance.
Implementation Method 1
a conductive contact structure that is continuous between a first epitaxial source or drain structure and a second epitaxial source or drain structure
Implementation Method 2
using directed self-assembly to self-align stitches
Data Source
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AI summary
Integrated circuit structures having backside contact stitching are described. In an example, an integrated circuit structure includes a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires. First and second epitaxial source or drain structure are at respective ends of the first and second pluralities of horizontally stacked nanowires. A conductive contact structure is beneath and in contact with the first epitaxial source or drain structure and the second epitaxial source or drain structure, and the conductive contact structure is continuous between the first and second epitaxial source or drain structures. The conductive contact structure has a first vertical thickness beneath the first and second epitaxial source or drain structures greater than a second vertical thickness in a region between the first and second epitaxial source or drain structures.