Backside Contact Assembly Stress Reduction in 3D Memory
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Solution Overview
Problem
Three-dimensional memory devices face challenges in wafer warpage due to stress induced by local variations in material composition, which complicates subsequent processing steps like chip bonding and packaging, and conventional methods to minimize stress are not always effective.
Innovation Solution
The implementation of a three-dimensional memory device design that includes a pair of alternating insulating and conductive layers with a backside contact assembly, featuring an isolation dielectric spacer, a conductive liner, and a composite non-metallic core to distribute stress evenly and reduce warpage, achieved through specific processing steps such as forming vertically alternating sequences, replacing sacrificial material layers, and creating backside trenches and contact assemblies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional stress minimization methods are used, then manufacturing simplicity is maintained, but wafer warpage is not effectively reduced
Solution Approach 1:
The backside contact assembly is segmented into multiple functional components: isolation dielectric spacer, conductive liner, and composite non-metallic core. This segmentation allows each component to address specific stress management requirements, enabling effective warpage reduction through distributed stress control rather than a single complex structure.
Solution Approach 2:
The backside contact assembly employs composite non-metallic core material that combines different dielectric materials with complementary stress properties. This composite structure enables balancing of stress in both x and y directions, effectively reducing wafer warpage while maintaining manufacturability through standardized processing steps.
2Manufacturing precision
If stress is reduced through material composition optimization, then wafer warpage is minimized, but processing complexity increases
Solution Approach 1:
The backside contact assembly is formed using preliminary action by establishing the isolation dielectric spacer and conductive liner structures before final stress balancing is required. This sequence allows subsequent stress management through the composite core material without requiring rework of previously formed structures, maintaining processing ease while achieving wafer flatness.
Solution Approach 2:
The composite non-metallic core utilizes parameter changes in dielectric material properties to balance stress in both x and y directions. By selecting materials with specific stress characteristics and arranging them in a composite structure, the system achieves effective warpage reduction through material parameter optimization rather than complex processing steps.
3Manufacturing precision
If backside contact assembly with composite core is implemented, then wafer warpage is effectively reduced, but device structure becomes more complex
Solution Approach 1:
The backside contact assembly is segmented into distinct functional zones: the isolation dielectric spacer for structural support, the conductive liner for electrical connectivity, and the composite non-metallic core for stress management. This segmentation enables each component to be optimized independently while maintaining overall simplicity through modular construction.
Solution Approach 2:
The backside contact assembly achieves multi-functionality by integrating stress balancing, electrical conduction, and structural isolation within a single assembly structure. The composite non-metallic core simultaneously balances stress in both x and y directions while the conductive liner provides electrical connectivity, reducing the need for additional separate structures and maintaining device simplicity.
Data Source
AI summary
A three-dimensional memory device includes a pair of alternating stacks of insulating layers and electrically conductive layers located over a semiconductor region, and laterally spaced from each other by a backside trench, memory stack structures extending through the pair of alternating, each memory stack structure containing a vertical semiconductor channel and a memory film, and a backside contact assembly located in the backside trench. The backside contact assembly includes an isolation dielectric spacer contacting the pair of alternating stacks, a conductive liner contacting inner sidewalls of the isolation dielectric spacer and a top surface of the semiconductor region, and composite non-metallic core containing at least one outer dielectric fill material portion that is laterally enclosed by a lower portion of the conductive liner and a dielectric core contacting an inner sidewall of the at least one outer dielectric fill material portion.