Backside Contact Integration With Thick Silicon for Tight N2P Spacing
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Solution Overview
Problem
The integration of backside power delivery networks in integrated circuits faces challenges due to the placement of backside power rails and contacts, particularly in architectures with both logic and passive device regions, leading to increased active region spacing requirements and difficulties in accessing backside placeholders.
Innovation Solution
A two-step backside placeholder process is introduced, involving the formation of a thick silicon layer over a first backside placeholder and growing a second backside placeholder epitaxy to a shallow trench isolation thickness, ensuring sufficient n-well height and preventing n-well squeezing, while allowing for tight active region spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If backside power delivery network is integrated with conventional placeholder placement, then power delivery is achieved, but active region spacing increases and current drive capability is reduced
Solution Approach 1:
The patent moves the power delivery network from the front side to the back side of the semiconductor substrate, utilizing the third dimension (depth/substrate thickness) to resolve the spacing conflict. By forming backside contacts through the substrate thickness, the design achieves tight active region spacing on the front side while maintaining adequate power delivery spacing on the back side.
Solution Approach 2:
The patent segments the power delivery function into separate backside contacts that are spatially distinct from the active regions. The first and second backside placeholders are positioned to provide independent power delivery paths, allowing the active regions to be closely spaced without compromising power delivery reliability.
2Ease of manufacture
If backside contacts are formed with uniform dimensions, then manufacturing is simplified, but n-well squeezing occurs and current drive capability is reduced
Solution Approach 1:
The patent employs asymmetric contact formation where the first backside placeholder has a first thickness and the second backside placeholder has a second thickness greater than the first. This asymmetric design prevents n-well squeezing in critical regions while maintaining manufacturability through a systematic two-step process that accommodates different thickness requirements.
Solution Approach 2:
Different regions of the backside contacts are given different thicknesses based on their specific functional requirements. The second backside placeholder has increased thickness in regions where n-well support is critical, while other regions maintain standard thickness, optimizing both device performance and manufacturing feasibility.
3Productivity
If thick silicon layer is used for backside contact integration, then active region spacing is reduced, but access to backside placeholders becomes difficult
Solution Approach 1:
The patent performs preliminary actions by forming the first backside placeholder with initial thickness, then adding a thick silicon layer, and subsequently forming the second backside placeholder with increased thickness. This sequential approach prepares the structure in advance to accommodate both tight active region spacing and adequate placeholder access through the thickened regions.
Solution Approach 2:
The thick silicon layer acts as an intermediary that enables both tight active region spacing and adequate placeholder access. By strategically thickening the silicon layer in specific regions between the active regions and backside placeholders, the design mediates between the conflicting requirements of compact front-side layout and accessible back-side contacts.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates efficient backside contact integration with thick silicon layers, enabling tight active region spacing and reducing overlay variations, thereby improving power delivery and maintaining current drive capability.
Implementation Method 1
growing a second backside placeholder epitaxy to a shallow trench isolation thickness
Data Source
AI summary
Embodiments of the present disclosure are directed to processing methods and resulting structures for providing direct backside contact integrations with thick silicon layers to enable passive device and tight active region of NFET-to-active region of PFET (N2P) spacing. In a non-limiting embodiment, a method includes forming a backside contact electrically coupled to a first source or drain (S/D) region. The backside contact includes an upper portion and a lower portion. The lower portion has a larger critical dimension than the upper portion. A frontside contact is electrically coupled to a second S/D region and a backside contact dielectric liner conformally wraps around the upper portion and the lower portion of the backside contact.