Backside Contact Trench Isolation for Uniform Silicon Thickness
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Solution Overview
Problem
The miniaturization of transistors and increasing density on chips leads to inconsistent silicon thickness under source/drain regions and shallow trench isolation areas, causing resistance variations, high resistance in narrow width transistors, and potential latch-up issues, affecting the performance and reliability of semiconductor devices.
Innovation Solution
A semiconductor device with backside contact and uniform silicon thickness across regions, achieved by a backside power delivery network and dielectric layers isolating the backside contact from direct contact with source/drain regions and shallow trench isolation, ensuring consistent performance and preventing latch-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor miniaturization and density increase are pursued, then computational power and energy efficiency are enhanced, but silicon thickness inconsistency under source/drain regions and shallow trench isolation areas occurs, causing resistance variations and potential latch-up issues
Solution Approach 1:
The substrate is divided into multiple regions with different thickness characteristics: thinner regions under source/drain areas and thicker regions under shallow trench isolation areas. This segmentation allows each region to be optimized independently, maintaining uniform electrical characteristics despite varying physical thickness
Solution Approach 2:
Different silicon thicknesses are implemented in different locations based on local requirements. The substrate thickness is locally adjusted to compensate for variations in source/drain and shallow trench isolation regions, ensuring consistent electrical performance across the chip
2Power
If backside contact structure is implemented, then power delivery network efficiency is improved, but direct contact between backside contact and source/drain regions may cause latch-up issues
Solution Approach 1:
An intermediate dielectric layer is introduced between the backside contact and the source/drain regions. This dielectric layer acts as a mediator that prevents direct electrical contact and potential latch-up while still allowing the backside contact to deliver power efficiently through the substrate
Solution Approach 2:
The harmful direct electrical contact pathway is extracted or removed from the structure. By eliminating the direct connection between backside contact and source/drain regions, the latch-up risk is removed while preserving the beneficial power delivery function
Data Source
AI summary
A semiconductor device includes a logic device including a first portion of a first substrate extending vertically below a first source/drain region, a second portion of the first substrate extending vertically below a second source/drain region, a first shallow trench isolation (STI) extending vertically and isolating the first portion of the first substrate and the second portion of the first substrate, a backside power delivery network (BSPDN) below the logic device, a first dielectric layer extending vertically through sidewalls of a backside contact. The first dielectric layer isolates the backside contact from the first portion of the first substrate and the second portion of the first substrate.