Backside Contact Cavity Wet Etch to Prevent Voids and Seams

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Solution Overview

Problem

As transistors reduce in size to increase device density, the formation of backside contacts in integrated chips can lead to voids and seams due to the widening of trenches, affecting the reliability and efficiency of the transistor devices.

Innovation Solution

A second removal process using a wet etch is performed to form a cavity below the channel structures, which has a larger maximum width than the trench, allowing the backside contact to have a width that continuously decreases from the backside of the transistor device towards the source/drain region, thereby mitigating voids and seams.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If transistors are reduced in size to increase device density, then device density is improved, but the formation of backside contacts leads to voids and seams affecting reliability

Engineering Contradiction:
Improvedevice densityVSAvoidbackside contact reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a vertical cavity dimension beneath the transistor channel structures to accommodate the backside contact. By extending the contact formation into the vertical dimension (below the channel structures) rather than only in the horizontal plane, the design allows for a continuous width profile that eliminates voids and seams while maintaining high device density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The cavity is formed in advance before the backside contact is deposited. This preliminary action creates a pre-configured space with the proper width profile, ensuring that when the conductive material is later deposited, it forms a seamless continuous structure without voids or seams.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If a trench is widened to form backside contact, then contact formation is enabled, but voids and seams are created reducing reliability

Engineering Contradiction:
Improvebackside contact formationVSAvoidcontact integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the width parameter of the cavity along the vertical direction, creating a continuous width profile that decreases from the backside of the transistor device towards the source/drain region. This continuous parameter variation eliminates abrupt discontinuities that would cause voids and seams, while still enabling proper contact formation.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The cavity width transitions smoothly rather than abruptly, creating a curved or tapered profile instead of sharp corners or discontinuities. This smooth transition prevents stress concentration and material defects, eliminating voids and seams in the backside contact structure.

Inventive Principle:
Principle #14Spheroidality (Curvature)

3Reliability

If cavity width is increased beyond trench width, then voids and seams are mitigated, but manufacturing complexity increases

Engineering Contradiction:
Improvecontact defect reductionVSAvoidcavity formation process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The cavity formation process is segmented into distinct steps: first forming the cavity with a maximum width greater than the trench width, then subsequently forming the backside contact within this pre-configured cavity. This segmentation allows each step to be optimized independently, managing manufacturing complexity while achieving the desired continuous width profile.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability of the backside contact and increases device density by reducing defects, allowing for more efficient and reliable transistor operation.

Implementation Method 1

A second removal process using a wet etch is performed to form a cavity below the channel structures

Methodology Applied
Scientific EffectWet etch:

Data Source

PatentUS11942527B2Forming a cavity with a wet etch for backside contact formation
Publication Date: 2024.03.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11942527B2 patent drawing
  • US11942527B2 patent drawing
  • US11942527B2 patent drawing

AI summary

In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.