Backside Contact Structure With Wide Base for Void-Free Power Rails
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Solution Overview
Problem
Conventional methods for forming direct backside contacts (DBC) in semiconductor devices face challenges such as patterning issues and high aspect ratio etch processes, leading to void formation and alignment difficulties, especially as contacted poly pitch becomes narrower.
Innovation Solution
A semiconductor device structure is developed with a backside power delivery network (BSPDN) that omits a bottom dielectric isolation layer, featuring a direct backside contact (DBC) with a positive etch slope and a dielectric material barrier on the sidewall, allowing for void-free alignment and improved electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional direct backside contact (DBC) methods are used, then power distribution is achieved, but patterning issues and alignment difficulties occur, leading to void formation
Solution Approach 1:
The patent introduces a sacrificial layer that is formed and patterned before the actual DBC structure. This preliminary structure guides the subsequent formation of the DBC, ensuring proper alignment and preventing voids by providing a template for the contact hole placement and dimensions.
Solution Approach 2:
The sacrificial layer acts as an intermediary element between the patterning process and the final DBC structure. It mediates the alignment process by providing a temporary reference structure that is removed after serving its alignment function, thereby eliminating the root cause of alignment precision issues.
2Productivity
If narrow contacted poly pitch is used, then device integration is improved, but void formation and alignment difficulties increase in DBC processes
Solution Approach 1:
The sacrificial layer is formed with the narrow pitch pattern first, serving as a preliminary structure that defines the precise locations and dimensions of the DBC contacts. This preliminary patterning enables narrow pitch implementation while maintaining manufacturing precision through the sacrificial template.
Solution Approach 2:
The patent changes the physical and chemical parameters of the sacrificial layer (material composition, thickness, etch selectivity) to optimize its function as a pattern template. These parameter changes enable the sacrificial layer to maintain structural integrity during processing while allowing precise pattern transfer to the final DBC structure.
3Length of moving object
If high aspect ratio etch processes are used for DBC, then contact depth is achieved, but void formation occurs
Solution Approach 1:
The sacrificial layer serves as an intermediary etch stop and filling template that prevents void formation during high aspect ratio etching. By controlling the etch process through the sacrificial layer's physical presence and subsequent removal, the patent achieves full contact depth while maintaining contact integrity without voids.
Solution Approach 2:
The sacrificial layer is prepared in advance with optimal dimensions and material properties that enable it to serve as an etch stop and filling reference. This preliminary preparation ensures that the high aspect ratio etch process can proceed to full depth without creating voids, as the sacrificial layer provides a controlled termination point and filling guide.
Data Source
AI summary
Semiconductor devices are provided. A semiconductor device includes a source/drain (S/D) region. The semiconductor device includes a backside (BS) contact that includes an upper surface that is on a lower surface of the S/D region. Moreover, the semiconductor device includes a BS power rail that is on a lower surface of the BS contact and is electrically connected to the S/D region by the BS contact. The lower surface of the BS contact is wider than the upper surface of the BS contact. Related methods of forming semiconductor devices are also provided.