Self-Aligned Backside Contacts for Nanosheet Logic-Passive Integration
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Solution Overview
Problem
Fabricating self-aligned backside contacts for nanosheet transistor structures with tight N2P spacing poses challenges, particularly in maintaining silicon substrate continuity beneath and below passive devices while avoiding electrical shorts and increased resistance.
Innovation Solution
A method for forming individual backside source drain contacts for logic devices while maintaining silicon substrate continuity beneath and below passive devices, using a novel approach that includes forming backside contact structures compatible with passive devices, including the use of dielectric layers and etch stop layers to separate and align contacts effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If self-aligned backside contacts are fabricated for nanosheet transistor structures with tight N2P spacing, then device integration and performance are improved, but maintaining silicon substrate continuity beneath passive devices becomes difficult and electrical shorts may occur
Solution Approach 1:
The patent divides the substrate into distinct logic device regions and passive device regions, applying different processing treatments to each. The logic region receives backside contact fabrication while the passive region maintains substrate continuity, resolving the contradiction through spatial segmentation of processing approaches.
Solution Approach 2:
The patent implements region-specific structures where the logic device region contains backside contact structures embedded in dielectric layers, while the passive device region maintains continuous silicon substrate. This local differentiation allows each region to have optimized properties for its specific function without compromising the other.
2Area of moving object
If backside contact structures are formed in tight N2P spaces, then device footprint is reduced, but electrical shorts between contacts increase
Solution Approach 1:
The patent introduces dielectric layers as intermediary materials between the backside contact structures and the substrate, and between adjacent contacts. These dielectric layers provide electrical isolation and prevent shorts while allowing the contacts to be positioned in tight spaces, thus enabling reduced footprint without compromising electrical isolation.
Solution Approach 2:
The patent moves contact structures to the backside of the substrate, utilizing the third dimension (vertical positioning) to achieve tight N2P spacing without compromising lateral electrical isolation. This dimensional transition allows contacts to be closely spaced while maintaining adequate isolation through the dielectric layer medium.
3Ease of manufacture
If conventional backside contact fabrication is used, then manufacturing process is simpler, but electrical resistance increases
Solution Approach 1:
The patent performs preliminary actions by forming dielectric layers and etch stop layers before creating the backside contact structures. This preliminary preparation enables precise control of contact depth and position, ensuring optimal electrical connection to the nanosheet channels while maintaining a systematic fabrication approach that balances simplicity with performance.
Solution Approach 2:
The patent controls and optimizes multiple parameters including dielectric layer thickness, etch stop layer positioning, and contact structure depth to achieve the desired electrical resistance characteristics. By carefully adjusting these parameters, the patent reduces electrical resistance while maintaining a feasible fabrication process.
Data Source
AI summary
A nanosheet semiconductor structure including a logic device region comprising logic devices having backside contact structures embedded in a backside dielectric layer, and a passive device region including passive devices on a continuous silicon substrate, where a height of the backside dielectric layer in the logic device region is substantially equal to a height of the continuous silicon substrate in the passive device region.