Self-Aligned Backside Contacts for Low-Rc Power Delivery
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Solution Overview
Problem
The formation of backside metal contacts in semiconductor devices faces challenges such as voids, Rc degradation, and reliability issues, along with alignment problems, which hinder the effective implementation of backside power rails for advanced semiconductor processing.
Innovation Solution
A semiconductor structure is developed with a dielectric layer and a bottom dielectric isolation layer forming an etch stop layer, allowing for self-aligned backside metal contacts through controlled etching, ensuring precise alignment and increased contact area, thereby improving Vmax and reducing contact resistance (Rc).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If backside metal contacts are formed to improve power delivery and density, then contact area and power delivery efficiency are improved, but metal fill issues (voids, Rc degradation) and alignment problems occur
Solution Approach 1:
The patent performs preliminary actions by forming the dielectric layer and etch stop layer on the front side of the substrate before flipping the substrate to form backside metal contacts. This preliminary structuring enables self-alignment during backside contact formation, preventing alignment errors while ensuring proper metal fill and reducing voids.
2Reliability
If backside metal contacts are formed to increase contact area, then power delivery is improved, but metal fill issues (voids, Rc degradation) occur
Solution Approach 1:
The patent introduces an etch stop layer as an intermediary between the dielectric layer and the substrate. This intermediary layer controls the etching process during backside contact formation, ensuring complete metal fill without voids while achieving low contact resistance through proper etch depth control.
3Device complexity
If conventional backside metal contact formation is used, then process integration is simplified, but overlay alignment and metal fill reliability deteriorate
Solution Approach 1:
The patent performs preliminary actions by forming the dielectric layer and etch stop layer on the front side of the substrate before flipping the substrate to form backside metal contacts. This preliminary structuring enables self-alignment during backside contact formation, preventing alignment errors while ensuring proper metal fill and reducing voids.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the formation of self-aligned backside metal contacts with controlled overlay shift and increased contact area, enhancing semiconductor device performance by improving Vmax and reducing contact resistance (Rc).
Implementation Method 1
the dielectric layer and bottom dielectric isolation layer form an etch stop layer, enabling controlled backside metal contact formation with high etch selectivity
Data Source
AI summary
A semiconductor structure includes a field effect transistor having a plurality of source/drain regions and a metal gate structure. A dielectric layer is in contact with a first surface of each of the plurality of source/drain regions, while a bottom dielectric isolation layer is in contact with a first surface of the metal gate structure. The bottom dielectric isolation layer is coplanar with the dielectric layer. The semiconductor structure further includes a backside metal contact that extends through a backside interlevel dielectric and the dielectric layer until an uppermost surface of at least one source/drain region of the plurality of source/drain regions. The backside interlevel dielectric is disposed above the dielectric layer and above the bottom dielectric isolation layer. The backside metal contact electrically connects the at least one source/drain region to a backside interconnect structure disposed above the backside interlevel dielectric.