Backside Transistor Contacts Using Local Interconnects to Ease MOL Congestion

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Dense device layouts in semiconductor devices with backside power distribution cause congestion at the middle-of-line layer, making it difficult to provide electrical contacts everywhere they are needed.

Innovation Solution

The implementation of local interconnects formed entirely within the interlayer dielectric, which connect transistors without bringing the contact up to the back-end-of-line, freeing space at shallower levels and allowing other interconnects to reach the conductive lines at the surface of the interlayer dielectric without crowding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If dense device layouts are used to increase transistor density, then productivity is improved, but congestion at the middle-of-line layer occurs making it difficult to provide electrical contacts

Engineering Contradiction:

Improvetransistor densityVSAvoidcongestion at middle-of-line layer

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces local interconnects formed entirely within the interlayer dielectric, creating a new dimensional pathway for electrical connections. This allows transistors to be connected through the dielectric layer without requiring congested middle-of-line interconnects, effectively adding a vertical dimension to the interconnection architecture and resolving the congestion problem while maintaining high transistor density.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Device complexity

If local interconnects are formed within the interlayer dielectric, then space at shallower levels is freed reducing congestion, but additional manufacturing steps are required

Engineering Contradiction:

Improvecongestion at middle-of-line layerVSAvoidfabrication process complexity

Core Design Contradiction:

Device complexityVSEase of manufacture

Solution Approach 1:

The patent merges the formation of local interconnects with the existing interlayer dielectric processing steps. The local interconnects are formed as part of the dielectric layer fabrication sequence, combining multiple functions (dielectric formation and interconnect creation) into a unified process flow, which reduces the impact of added complexity on the overall manufacturing process.

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If bottom vias have varying widths to accommodate different contact requirements, then electrical connectivity is improved, but manufacturing precision requirements increase

Engineering Contradiction:

Improveelectrical connectivityVSAvoidvia width control

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by varying the width of bottom vias only in specific regions where different contact requirements exist, while maintaining uniform width in other areas. This localized variation approach ensures that manufacturing precision challenges are confined to specific zones rather than affecting the entire structure, making the process more controllable while still achieving the required electrical connectivity.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250210518A1Direct backside contacts with local interconnects

Publication Date: 2025.06.26 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

Semiconductor devices include transistors in an active layer. Top vias are in electrical contact between top surfaces of the transistors and overlying frontside back-end-of-line (BEOL) layers. A local interconnect is in electrical contact between transistors underneath the transistors. Bottom vias are in electrical contact between bottom surfaces of the transistors and underlying backside BEOL layers.