Backside Source-Drain Contacts for Lower-Resistance Nanosheet Scaling
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, limiting further miniaturization beyond the 10 nanometer node, and requires new methodologies or integrated technologies to optimize performance and reduce edge placement errors and contact resistance.
Innovation Solution
A backside contact coloring scheme with single-pass front side processing enables independent etching, implantation, and metallization of NMOS and PMOS contacts, and a backside power delivery network that reduces cell height and power network resistance, allowing for reduced contact resistance and improved performance without altering front side processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling multi-gate transistors, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to variability limiting further miniaturization beyond 10 nanometer node
Solution Approach 1:
The fabrication process is divided into separate front-side and back-side operations. The backside contact coloring scheme segments the contact formation process into distinct steps for NMOS and PMOS contacts, allowing independent optimization of each contact type while maintaining overall process control and precision at 10nm node and below.
Solution Approach 2:
The patent introduces backside contact formation as a new dimension of contact access, moving from traditional front-side only contact formation to include backside contacts. This dimensional change enables independent etching, implantation, and metallization of NMOS and PMOS contacts through the backside of the substrate, improving manufacturing precision without significantly increasing front-side process complexity.
2Area of moving object
If cell height is reduced for scaling, then area density is improved, but edge placement errors increase
Solution Approach 1:
The backside contact structure acts as an intermediary element that decouples the relationship between cell height reduction and edge placement accuracy. By forming contacts through the backside, the patent enables precise contact alignment independent of front-side edge placement, allowing cell height scaling without proportionally increasing edge placement errors.
3Area of moving object
If contact dimensions are reduced for scaling, then device density is improved, but contact resistance increases
Solution Approach 1:
The patent transitions from planar contact formation to three-dimensional backside contact formation. This dimensional change allows contacts to extend vertically through the substrate thickness, increasing the effective contact area and reducing contact resistance even as the lateral contact footprint is reduced for scaling. The backside contact approach enables independent optimization of contact dimensions without the direct trade-off between contact area and resistance.
Data Source
AI summary
Integrated circuit structures having backside source or drain contact selectivity are described. In an example, an integrated circuit structure includes a first epitaxial source or drain structure at an end of a first plurality of horizontally stacked nanowires or fin, with a first conductive source or drain contact vertically beneath and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material beneath and in contact with the first conductive source or drain contact. A second epitaxial source or drain structure is at an end of a second plurality of horizontally stacked nanowires or fin, with a second conductive source or drain contact vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and a second hardmask material beneath and in contact with the second conductive source or drain contact.