Backside Self-Aligned Contacts for FinFET Power Rail Alignment
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Solution Overview
Problem
The semiconductor industry faces challenges with backside power rails in advanced technologies, such as shorting, leakage, routing resistance, alignment margins, layout flexibility, and packing density, particularly in multi-gate transistors like FinFETs and GAA FETs, due to the scaling down of device sizes and increased complexity.
Innovation Solution
A semiconductor structure with self-aligned backside power rails and vias is developed, where the backside via is electrically connected to the source feature of a field-effect transistor, eliminating overlay shifting and shorting issues, and an interconnect structure on the frontside reduces the number of power lines, allowing for more space for metal routing and processing margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device sizes are scaled down to increase functional density, then production efficiency and cost are improved, but alignment margins are reduced and manufacturing complexity increases
Solution Approach 1:
The patent moves power rail connections from the frontside to the backside of the substrate, utilizing the third dimension (vertical stacking) to resolve alignment conflicts. By forming backside power rails and self-aligned vias, the design separates power routing from signal routing planes, eliminating overlay shifting issues between power and signal features while maintaining scaled device dimensions.
Solution Approach 2:
The self-aligned via structure allows the via to automatically position itself relative to the source/drain feature through the same etch and deposition processes, eliminating the need for separate alignment steps. This self-alignment mechanism compensates for reduced alignment margins by making the via position dependent on the source/drain feature geometry rather than requiring independent alignment precision.
2Adaptability or versatility
If backside power rails are implemented in advanced technologies, then routing flexibility is improved, but shorting and leakage issues occur
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary between the backside power rail and the substrate, and another dielectric layer as an intermediary between the via and the source/drain feature. These intermediary dielectric layers provide electrical isolation that prevents shorting and leakage while allowing the power rail to maintain close proximity to the active device for low resistance connection.
3Adaptability or versatility
If conventional backside power rails are used, then layout flexibility is improved, but alignment shifting and shorting occur
Solution Approach 1:
The self-aligned via is formed by depositing conductive material conformally on the via structure before etching, and then performing a single etch step that defines both the via opening and the power rail contact. This preliminary conformal deposition establishes the via position relative to the source/drain feature before any alignment-critical etching occurs, preventing overlay shifting.
4Productivity
If device pitches are shrunk to increase packing density, then functional density is improved, but contact alignment and routing become more difficult
Solution Approach 1:
By moving the power connection to the backside of the substrate and using self-aligned vias, the patent eliminates the need for precise lateral alignment between power contacts and source/drain features. The vertical via structure replaces the lateral alignment requirement, allowing smaller device pitches without proportionally reducing alignment margins.
Data Source
AI summary
A method includes forming a fin over a semiconductor layer, depositing an isolation feature on sidewalls of the fin, recessing a portion of the fin to form a first trench exposing a top surface of the semiconductor layer, forming a sacrificial feature in the first trench, forming an epitaxial feature over the sacrificial feature, exposing a bottom surface of the sacrificial feature, removing the sacrificial feature to form a second trench exposing a bottom surface of the epitaxial feature, and forming a conductive feature in the second trench. The conductive feature electrically couples to the epitaxial feature.