Spacer-Guided Backside Contacts for Scaled Nanowire ICs
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Solution Overview
Problem
The variability in conventional fabrication processes limits the scalability of multi-gate transistors to the 10 nanometer node or sub-10 nanometer range, necessitating new methodologies for integrated circuit fabrication, particularly in forming backside conductive contacts and power delivery networks in semiconductor devices.
Innovation Solution
The implementation of spacer-guided backside conductive contacts and backside power delivery networks, which involve forming conductive contacts and power delivery interconnects from the backside of the wafer, reducing front-side processing complexity and enhancing process robustness, while allowing for self-aligned contact formation and reduced resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for multi-gate transistors, then existing infrastructure compatibility is maintained, but manufacturing precision and scalability to 10nm node are limited
Solution Approach 1:
The fabrication process is divided into separate front-side and backside operations. The backside contact formation is segmented as an independent process module, allowing each side to be optimized separately. This segmentation enables the use of specialized backside processing techniques without complicating the front-side transistor fabrication, thereby improving manufacturing precision while managing overall process complexity.
Solution Approach 2:
The patent transitions from traditional front-side-only contact formation to backside contact formation, adding a new dimensional aspect to the fabrication process. By moving contact formation to the backside of the wafer, the process achieves better precision for 10nm node devices without increasing front-side process complexity, as the backside processing operates in a separate spatial dimension.
2Reliability
If front-side contact formation is used, then layout flexibility is maintained, but processing defects and resistance increase
Solution Approach 1:
The patent inverts the traditional approach by forming contacts from the backside of the wafer rather than from the front side. This inversion allows contact holes to be formed through the substrate to reach front-side contacts, improving reliability by enabling better alignment and reduced processing defects. The self-aligned nature of backside contact formation simplifies the manufacturing process despite the inverted approach.
3Manufacturing precision
If backside conductive contacts are formed without spacer guidance, then manufacturing simplicity is maintained, but manufacturing precision and alignment accuracy deteriorate
Solution Approach 1:
The patent introduces spacers as intermediary structures that bridge the gap between lithographically defined patterns and final contact positions. These spacers act as self-aligned masks and guides during the contact hole formation process, ensuring high alignment precision without requiring complex lithographic steps. The spacers mediate between the front-side transistor structures and backside contact formation, improving manufacturing precision while adding only moderate process complexity.
4Productivity
If device dimensions are scaled down to increase density, then capacity increases, but process constraints become overwhelming
Solution Approach 1:
The patent addresses scaling constraints by moving contact formation operations to the backside of the wafer, effectively using the third dimension (wafer thickness) to resolve front-side space constraints. This dimensional transition allows higher device density on the front side without proportionally increasing process complexity, as backside processing operates independently and can be optimized separately for scaled dimensions.
Data Source
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AI summary
Integrated circuit structures having spacer-guided backside conductive contacts are described. An integrated circuit structure includes a first plurality of horizontally stacked nanowires or fin laterally spaced apart from a second plurality of horizontally stacked nanowires or fin. A first gate stack is over the first plurality of horizontally stacked nanowires or fin, and a second gate stack over the second plurality of horizontally stacked nanowires or fin. A front side conductive contact is between the first gate stack and the second gate stack. An epitaxial source or drain structure is over the front side conductive contact, the epitaxial source or drain structure between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin. A backside conductive contact (146) is over the epitaxial source or drain structure.