Backside Source/Drain Contacts for Scaled Nanowire Transistors
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits, particularly tri-gate transistors, is limited by variability in conventional fabrication processes, which hinders further reduction to the 10 nanometer node or below, and existing methods for backside power delivery in semiconductor devices face challenges such as increased cell area and process complexity.
Innovation Solution
The implementation of direct backside source or drain contacts through increased source/drain depth and backside gate recess, along with self-aligned access features, allows for simplified process flows and reduced parasitic capacitance, enabling efficient power delivery and reduced standard cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for multi-gate transistor scaling, then existing infrastructure compatibility is maintained, but manufacturing precision deteriorates at 10 nanometer node or below
Solution Approach 1:
The patent introduces backside contact architecture that accesses source/drain regions from the substrate backside rather than front side, adding a vertical dimension to the contact path. This dimensional change enables new fabrication approaches including backside gate recess and self-aligned access features, achieving 10nm node precision while managing fabrication complexity through alternative process routes
2Power
If backside power delivery is implemented, then power delivery efficiency is improved, but device complexity increases due to additional access features
Solution Approach 1:
The patent merges power delivery and signal functions by implementing backside contacts that serve dual purposes: providing power delivery while also serving as signal contacts. The self-aligned access features combine multiple structural elements into unified formations, reducing overall device complexity despite the advanced backside power delivery architecture
Solution Approach 2:
The self-aligned access features automatically position contact structures relative to gate and source/drain regions through the backside gate recess geometry itself, eliminating the need for additional alignment steps or complex positioning mechanisms, thereby reducing device complexity while maintaining power delivery efficiency
3Object-generated harmful factors
If source/drain depth is increased for direct backside contact, then parasitic capacitance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The backside gate recess is formed in advance before source/drain deposition, pre-establishing the geometric configuration that will guide subsequent self-aligned access feature formation. This preliminary action sets the depth and positioning parameters that automatically control the final source/drain contact geometry, reducing the need for precise depth control during later manufacturing steps
Data Source
AI summary
Integrated circuit structures having direct backside source or drain contacts are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure over and electrically coupled to a corresponding conductive backside contact that extends laterally beyond the first epitaxial source or drain structure without contacting the first gate stack or the second gate stack. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin.