Backside Source/Drain Contacts With Buried Features for Self-Alignment
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Solution Overview
Problem
The semiconductor industry faces challenges in managing complex metal layer routing in intermetal connection layers as minimum feature size reduces, necessitating innovative solutions for semiconductor device manufacturing.
Innovation Solution
The implementation of backside source/drain contacts formed using a buried source/drain feature and a semiconductor cap layer, enabling self-aligned contact formation and backside isolation while preventing voids in source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional front-side source/drain contacts are used, then metal layer routing complexity increases as minimum feature size reduces, but the manufacturing process remains relatively simple
Solution Approach 1:
The patent moves source/drain contacts from the traditional front-side (planar) dimension to the backside of the substrate, utilizing the third dimension (depth/substrate thickness) to resolve routing complexity. By forming contacts through the substrate backside, the invention eliminates the need for complex intermetal routing layers while maintaining electrical connectivity, thus reducing device complexity without significantly worsening manufacturing ease.
2Manufacturing precision
If backside source/drain contacts are formed, then contact alignment precision improves through self-alignment, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming buried source/drain features and semiconductor cap layers before substrate thinning and backside contact formation. The semiconductor cap layer is deposited over the buried source/drain features to protect them and establish precise alignment references. This preliminary structuring enables self-aligned backside contact formation, where the contact openings automatically align with the source/drain regions through the cap layer, improving manufacturing precision while the added process steps are managed through systematic sequencing.
Solution Approach 2:
The semiconductor cap layer serves as an intermediary element between the buried source/drain features and the backside contact openings. This cap layer mediates the alignment process by providing a protective and reference structure that enables precise self-alignment during backside contact formation, thus improving manufacturing precision while adding a manageable process step.
3Productivity
If substrate thinning is performed to expose buried source/drain features, then backside contact formation efficiency improves, but risk of creating voids in source/drain regions increases
Solution Approach 1:
The patent applies beforehand cushioning by depositing the semiconductor cap layer over the buried source/drain features before substrate thinning. This cap layer acts as a protective cushion that prevents void formation during the thinning and contact formation processes. The cap layer maintains structural integrity and provides a buffer that eliminates the risk of voids in the source/drain regions, thus improving reliability while enabling efficient backside contact formation.
Solution Approach 2:
The semiconductor cap layer serves as an intermediary protective structure during substrate thinning. It mediates between the thinning process and the buried source/drain features, preventing direct exposure and potential void formation. This intermediary layer ensures that the source/drain regions maintain their integrity throughout the backside contact formation process, improving reliability while maintaining productivity.
Data Source
AI summary
Embodiments of the present disclosure provide a semiconductor device with backside source/drain contacts formed using a buried source/drain feature and a semiconductor cap layer formed between the buried source/drain feature and a source/drain region. The buried source/drain feature and the semiconductor cap layer enable self-aligned backside source/drain contact and backside isolation. The semiconductor cap layer functions as an etch stop layer during backside contact formation while enabling source/drain region growth without fabrication penalty, such as voids in the source/drain regions.