Backside Source/Drain Contacts With SiGe Etch Stop for 10nm Scaling
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Solution Overview
Problem
The variability in conventional fabrication processes limits the scalability of integrated circuits to the 10 nanometer node or sub-10 nanometer range, particularly in multi-gate transistors, leading to challenges in further scaling and optimizing device performance.
Innovation Solution
Implementing direct backside source or drain contacts enabled by silicon germanium etch stop layers, which increase process margin and allow for direct patterning of contact vias to the source of the transistor from the backside, simplifying the process flow and enabling improved power delivery and reduced parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling, then existing process infrastructure can be maintained, but manufacturing precision and reliability deteriorate at 10 nanometer node or below
Solution Approach 1:
The patent introduces backside contact formation as a new dimensional approach to the conventional front-side fabrication process. By accessing the source/drain regions from the backside of the substrate, the process enables direct patterning of contact vias without relying on traditional front-side etching and alignment, thereby achieving the required precision at 10nm node and below while maintaining process reliability
2Productivity
If direct backside contact formation is implemented, then process flow is simplified and productivity increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming the silicon germanium etch stop layer at a predetermined depth during the initial substrate preparation stage, before contact via formation. This pre-positioned etch stop layer serves as a reliable depth reference that automatically ensures correct contact via depth and alignment, thereby simplifying the overall process flow while maintaining the required manufacturing precision without needing complex real-time control during via formation
3Reliability
If extensive over-etching is performed to ensure contact depth, then contact reliability is improved, but process complexity and time increase
Solution Approach 1:
The patent introduces the silicon germanium etch stop layer as an intermediary material positioned at the precise depth where contact vias should terminate. This intermediary layer acts as a physical stop that automatically prevents over-etching, ensuring consistent contact depth and reliability. The etch process naturally stops when it reaches this layer, eliminating the need for extensive over-etching and complex endpoint detection, thereby reducing both process time and complexity while maintaining contact reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the scalability of integrated circuits by simplifying the process flow, reducing the need for extensive over-etching, and improving electrical performance through uniform source/drain depth and reduced parasitic capacitance.
Implementation Method 1
enabled by silicon germanium etch stop layers, which increase process margin and allow for direct patterning of contact vias
Data Source
AI summary
Integrated circuit structures having direct backside source or drain contacts are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins, and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the epitaxial source or drain structure over and electrically coupled to a corresponding conductive backside contact that extends laterally beyond the epitaxial source or drain structure without contacting the first gate stack or the second gate stack.