Backside Gate and S/D Contacts With Sacrificial SiGe Isolation
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Solution Overview
Problem
The integration of power delivery networks in semiconductor chip architectures is challenging due to increasing device densities, particularly in backside-style architectures where forming backside contacts for gate, source, and drain regions is difficult due to poor margins and access, and introducing self-aligned contacts complicates the fabrication process.
Innovation Solution
The method involves forming additional sacrificial SiGe layers under the bottom dielectric isolation, which serve as buffer layers to allow silicon removal without damaging the source/drain epitaxy or gate, enabling the formation of backside dielectrics without device damage and providing additional process margin for contact patterning. Backside source/drain contacts are covered with a dielectric liner to isolate the backside gate contact, and a dielectric cap layer is used to isolate power and signal rails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If backside contacts for gate, source, and drain regions are formed through wafer backside in backside-style architecture, then power delivery network integration is achieved, but manufacturing precision deteriorates due to poor margins and access
Solution Approach 1:
Sacrificial SiGe layers are formed at the wafer backside before contact formation to create buffer zones. These preliminary structures enable subsequent contact patterning by providing etch stops and protecting underlying device structures, thereby improving manufacturing precision while maintaining backside contact capability
Solution Approach 2:
Dielectric liners are introduced as intermediary layers between the backside gate contact and backside source/drain contacts. These intermediary structures provide electrical isolation and prevent shorting, enabling reliable backside contact formation with improved manufacturing precision
2Manufacturing precision
If self-aligned contacts are introduced for backside contact formation, then contact alignment is improved, but device complexity increases
Solution Approach 1:
Multiple functions are merged into the dielectric liner structure: it serves as an etch stop, provides electrical isolation between contacts, and defines contact boundaries. This merging reduces the need for separate alignment-critical steps, thereby reducing fabrication process complexity while maintaining good contact alignment
Solution Approach 2:
The sacrificial SiGe layers serve multiple purposes: they act as etch stops during contact formation, protect underlying device structures from damage, and define contact locations. This multi-functionality simplifies the overall fabrication process while achieving self-aligned contact formation
3Ease of operation
If silicon is removed from wafer backside to form contacts, then contact access is improved, but device damage risk increases to source/drain epitaxy and gate
Solution Approach 1:
Sacrificial SiGe buffer layers are formed beforehand at the wafer backside to cushion and protect the underlying source/drain epitaxy and gate structures during silicon removal. These buffer layers absorb the mechanical and chemical stress of etching, preventing device damage while enabling adequate contact access
Solution Approach 2:
The sacrificial SiGe layers act as intermediary protective structures between the contact opening process and the sensitive device structures. They enable aggressive silicon removal for good contact access while mediating protection to prevent epitaxy and gate damage
Data Source
AI summary
Embodiments of the present invention are directed to processing methods and resulting structures for providing contacts for gate, source, and drain regions through a wafer backside. In a non-limiting embodiment of the invention, a front end of line structure having a gate and a source or drain (S/D) region is formed and a back end of line structure is formed on a first surface of the front end of line structure. The back end of line structure includes a backside S/D contact on a surface of the S/D region, a backside gate contact on a surface of the gate, and a backside contact liner in direct contact with a sidewall of the backside S/D contact and a sidewall of the backside gate contact. The backside gate contact is electrically isolated from the backside S/D contact by the backside contact liner.