Backside Source/Drain Contacts Using SiGe Sacrificial Layers
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Solution Overview
Problem
Existing technologies for fabricating complementary metal-oxide-semiconductor field effect transistors (CMOSFETs) with gate-all-around (GAA) structures face challenges in forming backside contacts and vias that are large enough to reduce resistance while avoiding short-circuits, particularly due to the decreased geometry size in advanced technology nodes.
Innovation Solution
The formation of silicon germanium (SiGe) layers below the source/drain features in the CFETs, allowing for the selective removal of these layers to create enlarged backside contacts and vias through a self-aligned process, thereby reducing resistance and avoiding short-circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to improve production efficiency and lower costs, then manufacturing productivity improves, but manufacturing precision deteriorates due to difficulty in forming large enough backside contacts and vias without short-circuits
Solution Approach 1:
The method performs preliminary actions by forming mandrels and spacers before final contact formation. The mandrels are positioned initially, then spacers are formed around them, and mandrels are selectively removed to create enlarged contact openings. This preliminary structuring enables precise control of backside contact dimensions without requiring direct patterning at the final small geometry scale.
Solution Approach 2:
The patent introduces intermediary structures (mandrels and spacers) that mediate between the patterning process and final contact formation. The mandrels serve as temporary intermediaries that define the initial position, while spacers act as intermediaries that determine the final contact size. These intermediaries enable indirect formation of contacts with dimensions larger than what direct patterning would allow at advanced technology nodes.
2Reliability
If backside contacts and vias are enlarged to reduce resistance, then electrical conductivity improves, but risk of short-circuits increases
Solution Approach 1:
The spacers perform a self-service function by automatically defining the boundaries of the backside contacts and vias. The spacer width directly determines the contact opening size, creating a self-aligned structure where the contact dimensions are controlled by the spacer formation process rather than requiring separate patterning steps. This self-service mechanism ensures consistent dimensions that balance conductivity needs with short-circuit prevention.
Solution Approach 2:
The patent applies local quality by selectively removing mandrels in specific regions to create enlarged contacts only where needed, while maintaining smaller dimensions in other areas. The selective mandrel removal allows different regions of the device to have optimally sized contacts tailored to their specific electrical requirements, achieving low resistance where necessary while maintaining isolation where critical.
3Manufacturing precision
If selective removal of SiGe layers is performed to create enlarged backside contacts, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The method utilizes parameter changes by exploiting the selective etchability of SiGe layers compared to surrounding materials. The SiGe mandrels and sacrificial layers are removed using etch processes that selectively target the germanium-containing layers, enabling clean removal without damaging adjacent structures. This parameter-based selectivity (etch rate differences) simplifies the removal step despite the added structural complexity.
Data Source
AI summary
A method of forming a semiconductor structure includes forming a fin structure over a substrate; forming first and second source/drain trenches in the fin structure; forming first and second SiGe layers in the first and second source/drain trenches, respectively; and forming first and second source/drain features over the first and second SiGe layers in the first and second source/drain trenches, respectively. The method further includes forming a first interlayer dielectric (ILD) layer on a backside of the substrate; etching the first ILD layer and the substrate to form a first opening that exposes the first SiGe layer; removing the first SiGe layer to form a second opening that exposes the first source/drain feature; and depositing a conductive material in the first and second openings to form a first source/drain contact. The lateral dimensions of the first opening are greater than those of the second opening.