Self-Aligned Backside Contacts With Protruding Source/Drain Epi
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Solution Overview
Problem
Existing semiconductor fabrication processes face challenges in achieving precise alignment of backside contacts without additional alignment steps, which can lead to defects and shorting due to misalignment, especially in high-performance devices.
Innovation Solution
The use of self-aligned backside contacts (SAB) with silicon germanium (SiGe)-based and silicon (Si)-based epitaxial protrusions through a backside interlayer dielectric (BILD) plane, eliminating the need for bottom dielectric isolation (BDI) and reducing misalignment risks by increasing the distance between source/drain contacts and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligned backside contact process is used, then alignment accuracy is improved, but manufacturing complexity increases due to multiple etching and CMP steps
Solution Approach 1:
The backside contact is self-aligned to the contact hole through the etching process itself. The BDI layer acts as a mask during etching, automatically positioning the backside contact in the correct location without requiring additional alignment steps or external intervention.
Solution Approach 2:
The BDI layer is formed beforehand to serve as a mask layer. This preliminary structure enables precise alignment of the contact holes to the active device regions during the etching process, ensuring accurate positioning before the actual contact formation occurs.
2Manufacturing precision
If BDI layer is used as mask, then alignment precision is improved, but device structure complexity increases
Solution Approach 1:
The BDI layer serves multiple functions: it acts as a mask during etching for precise alignment, provides electrical isolation between active device regions and the substrate, and enables the self-aligned backside contact formation. This multi-functionality reduces the need for additional separate structures.
Solution Approach 2:
The masking function and isolation function are merged into a single BDI layer structure. Instead of having separate mask layers and isolation layers, the BDI layer performs both roles simultaneously, simplifying the overall device structure while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy and reliability of contact formation, reducing defects and shorting risks while maintaining high-performance semiconductor device functionality.
Implementation Method 1
The PFET S/D may include a silicon germanium (SiGe)-based epi protruding through a BILD plane between a backside interlayer dielectric (BILD) and a first gate
Data Source
AI summary
Aspects of the present invention provide a semiconductor structure. The semiconductor structure may include a PFET source/drain (S/D). The PFET S/D may include a silicon germanium (SiGe)-based epi protruding through a BILD plane between a backside interlayer dielectric (BILD) and a first gate, and an NFET S/D. The NFET S/D may include a silicon (Si)-based epi protruding into the BILD plane and a SiGe epi between the BILD and the Si-based.