Multi-Part Backside Contacts for Stacked FET Short Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The close spacing between field effect transistors (FETs) in semiconductor devices can result in electrical shorts, particularly when forming contacts to stacked FETs with a backside power distribution network, leading to device inoperability due to tip-to-tip shorting between conductive interconnects.
Innovation Solution
A multi-part via structure is used to connect the top FET with a backside power distribution network, where the contact is made along the sidewall of the via, reducing lateral reach and increasing the contact area, thereby minimizing the risk of shorts and reducing electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the contact to the top FET extends laterally to reach the backside via, then electrical connection is achieved, but the contact comes close to adjacent FET contacts causing tip-to-tip shorting
Solution Approach 1:
The patent transitions from a traditional top-down contact approach to a backside contact approach, utilizing the vertical dimension to establish electrical connection. The contact structure extends from the backside of the substrate upward to reach the via, allowing lateral spacing between adjacent contacts while maintaining electrical connectivity through the vertical via path.
Solution Approach 2:
The patent introduces a via structure as an intermediary element that mediates the electrical connection between the top FET and the backside contact. This via acts as a bridge, allowing the contact to reach the FET through the substrate without requiring lateral extension that would cause shorting with adjacent contacts.
2Productivity
If contacts are formed with close spacing to accommodate stacked FETs, then device density increases, but electrical shorts between adjacent contacts occur
Solution Approach 1:
The patent resolves the spacing conflict by moving the contact formation to the backside dimension rather than relying on lateral spacing. This allows dense stacking of FETs in the lateral direction while maintaining adequate spacing between contacts in the vertical/backside direction, preventing shorts while achieving high device density.
Solution Approach 2:
The contact structure is segmented into multiple parts: a backside contact portion and a via portion that extends upward. This segmentation allows the contact to be positioned away from adjacent contacts at the backside while still achieving electrical connection to the FET through the via, thus preventing shorting while maintaining density.
3Ease of manufacture
If traditional top-down contacts are used, then fabrication is simpler, but lateral reach causes shorting with adjacent FET contacts
Solution Approach 1:
The patent inverts the traditional contact formation approach by making contacts from the backside of the substrate rather than from the top. This inversion allows the contacts to be formed with standard fabrication techniques while achieving a geometry that prevents lateral encroachment on adjacent FET contacts, eliminating the shorting problem.
Data Source
AI summary
Semiconductor devices include a top field effect transistor (FET) and a bottom FET. A first conductive via is in electrical connection with a first conductive interconnect beneath the bottom FET. A second conductive via is in electrical connection with the first conductive via. A backside top FET contact is in electrical connection with the top FET and with a side surface of the second conductive via.