Dual-Height Backside Contacts for Stacked Transistor Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As transistors with smaller physical dimensions are developed, the space for backside power rail connections and signal wire connections decreases, leading to potential instability and reduced performance if these connections are not strong and stable.
Innovation Solution
The method involves forming dual height backside contacts with backside through vias to accommodate tight spacing between power planes and power and signal wires. This is achieved by connecting a first backside contact to a bottom source/drain region and a frontside wiring, and a second backside contact to another bottom source/drain region and a backside power plane, with a connection via formed through the power plane to connect a top source/drain region to a backside power rail.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors with smaller physical dimensions are used, then transistor density and processing speed are improved, but space for backside power rail connections and signal wire connections decreases
Solution Approach 1:
The patent utilizes the vertical dimension by forming backside contacts at different heights (dual-height contacts) and routing connections through multiple layers including through-silicon vias. This allows power and signal connections to be established in the vertical space rather than competing for horizontal space, enabling smaller transistor footprints while maintaining adequate connection space.
Solution Approach 2:
The backside contact structure is segmented into multiple components including first and second backside contacts at different heights, through-silicon vias, and separate power rail connections. This segmentation allows each connection element to be optimized independently for its specific function, enabling dense packing while maintaining strong electrical connections.
2Use of energy by moving object
If transistors with smaller physical dimensions are used, then energy efficiency is improved, but connection stability may deteriorate
Solution Approach 1:
By moving connection stability concerns into the vertical dimension with multi-layer routing and through-silicon vias, the patent isolates the small-footprint transistors from connection reliability issues. The extended vertical connection paths provide multiple bonding interfaces and larger effective connection areas despite small horizontal transistor dimensions.
Solution Approach 2:
The patent incorporates redundant connection paths and multiple contact points before potential connection failures can occur. The dual-height backside contacts and through-silicon via structure provide backup connection routes that compensate for potential weaknesses in individual connection points, ensuring reliability for small transistors.
Data Source
AI summary
Embodiments of the present disclosure include a semiconductor device having stacked transistors with a bottom transistor below a top transistor, the bottom transistor having a first bottom source/drain region and a second bottom source/drain region. A first backside contact is connected to the first bottom source/drain region and a frontside wiring. A second backside contact is connected to the second bottom source/drain region and a backside power plane. A connection via is formed through the backside power plane to connect a top source/drain region of the top transistor to a backside power rail.