Backside Coolant Channel Assembly for High-Power Semiconductor Cooling
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Solution Overview
Problem
Existing cooling systems for microelectronic devices face challenges in managing high power density, as frontside power/ground delivery networks occupy valuable space and interfere with thermal dissipation, while backside delivery networks can disrupt thermal pathways, making it difficult to meet thermal budgets in large-scale computing systems.
Innovation Solution
Integrated cooling systems with a power/ground delivery network on the backside of the device, utilizing a cold plate with conductive layers and thru-substrate interconnects that do not interfere with thermal pathways, allowing for efficient power delivery and enhanced thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power/ground delivery network is disposed on the frontside, then power delivery capability is improved, but valuable chip area is occupied and thermal dissipation is interfered with
Solution Approach 1:
The patent inverts the conventional approach by moving the power/ground delivery network from the frontside to the backside of the chip. This inversion allows the active side to be fully dedicated to high power-density circuitries while the backside handles power delivery, thus resolving the area conflict and thermal interference issues.
Solution Approach 2:
The patent utilizes the third dimension (vertical stacking) by implementing power delivery through the backside of the chip rather than competing for planar space on the frontside. This dimensional transition enables both power delivery and active circuitry to coexist without spatial conflict.
2Area of stationary object
If power/ground delivery network is disposed on the backside, then chip area is preserved, but thermal dissipative systems are interfered with
Solution Approach 1:
The patent applies local quality by creating distinct functional zones on the backside: regions with power delivery networks and regions with thermal dissipative structures. This spatial differentiation allows both power delivery and thermal management to coexist without mutual interference, addressing the thermal conflict while preserving backside area.
3Power
If frontside power delivery is used, then power delivery is achieved, but signal routing space is reduced
Solution Approach 1:
The patent segments the chip into functionally distinct sides: the frontside is dedicated to active circuitry and signal routing, while the backside is dedicated to power delivery. This segmentation eliminates the competition for routing space and allows each side to be optimized independently for its specific function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces thermal resistance and enables effective power delivery without interfering with thermal pathways, improving the cooling efficiency and thermal management in high-power density microelectronic devices.
Implementation Method 1
a coolant channel therebetween
Implementation Method 2
coolant channel
Data Source
AI summary
The present disclosure provides for integrated cooling systems including backside power delivery and methods of manufacturing the same. An integrated cooling assembly may include a device and a cold plate. The cold plate has a first side and an opposite second side, the first side having a recessed surface, sidewalls around the recessed surface that extend downwardly therefrom to define a cavity, and a plurality of support features disposed in the cavity. The first side of the cold plate is attached to a backside of the device to define a coolant channel therebetween. The cold plate includes a substrate, a dielectric layer disposed on a first surface of the substrate, a first conductive layer disposed between the first surface and the dielectric layer, a second conductive layer disposed on a second surface of the substrate, and thru-substrate interconnects connecting the first conductive layer to the second conductive layer.