Backside Cross-Coupled Interconnects for Denser IC Routing
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Solution Overview
Problem
The challenge in integrated circuit fabrication is the efficient use of space in high-density semiconductor devices, particularly in forming connections between transistor elements, which is complicated by the presence of local interconnect layers that occupy valuable space.
Innovation Solution
The implementation of backside interconnect structures that replace frontside local interconnect layers, allowing for the connection of transistor elements such as source or drain regions and gate structures, thereby freeing up space in the interconnect region for other signal tracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If local interconnect layers are used to connect transistor elements, then electrical connections between source/drain regions and gates are established, but valuable space in the interconnect region is occupied
Solution Approach 1:
The patent moves interconnect structures from the frontside (top surface) to the backside (bottom surface) of the semiconductor device, utilizing the third dimension (depth/thickness) to resolve the space conflict. By forming conductive structures that extend through the substrate thickness to contact transistor elements from below, the interconnect region on the frontside is freed up while maintaining all necessary electrical connections.
2Quantity of substance
If device spacing is reduced at the device layer, then higher density semiconductor devices are achieved, but routing multiple logic signals becomes more difficult
Solution Approach 1:
The patent resolves signal routing complexity by transitioning from planar (2D) routing on the frontside to vertical (3D) routing through the substrate. Conductive structures extend downward through the substrate to reach transistor elements, enabling signal routing in the depth dimension. This allows closely spaced devices to be interconnected without requiring complex lateral routing paths.
Solution Approach 2:
The patent segments the interconnect function into separate layers: frontside interconnect structures for certain signals and backside interconnect structures for other signals. This segmentation allows independent optimization of each interconnect layer, simplifying the routing of multiple logic signals by distributing them across different spatial domains (frontside vs. backside).
Data Source
AI summary
Techniques are provided herein to form an integrated circuit having a backside interconnect structure coupled between different transistor elements, such as between source or drain regions and/or gate structures. The backside interconnect structure may be used to replace frontside local interconnect structures, thus freeing up more space in the frontside interconnect region. In one such example, a first semiconductor device includes a first semiconductor region extending from a first source or drain region and a first gate structure extending over the first semiconductor region, and a second semiconductor device includes a second semiconductor region extending from a second source or drain region and a second gate structure extending over the second semiconductor region. A conductive structure is coupled between a bottom surface of each of the first source or drain region, the second source or drain region, and a portion of the first gate structure.