Backside-Connected Decoupling Capacitors for Dense IC Power Rails
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of integrating decoupling capacitors in densely packed integrated circuits with limited available footprint, as traditional MIM capacitors require significant space and additional processing steps, increasing cost and complexity.
Innovation Solution
The use of capacitors with backside contacts that are formed laterally adjacent to the device layer, utilizing parallel conductive plates with dielectric material between each pair, allowing connections to power or signal lines through backside contacts, which can be used as decoupling capacitors to filter AC noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional MIM capacitors are used for decoupling, then decoupling function is achieved, but the required footprint area increases significantly
Solution Approach 1:
The patent transitions from planar capacitor layouts to three-dimensional stacked capacitor structures. Multiple capacitor plates are stacked vertically with dielectric layers between them, utilizing the vertical dimension to increase capacitance density. This allows achieving the required decoupling capacitance within a smaller footprint area by stacking capacitor elements in the depth direction rather than spreading them out laterally.
Solution Approach 2:
The patent implements nested capacitor structures where multiple capacitor plates and dielectric layers are stacked within each other in a compact arrangement. The capacitor plates are positioned in alternating layers with dielectric material, creating a nested configuration that maximizes capacitance within a confined vertical space, thereby reducing the horizontal footprint area.
2Reliability
If traditional MIM capacitors are used, then decoupling capability is provided, but additional processing steps and manufacturing complexity increase
Solution Approach 1:
The patent combines the formation of capacitor structures with the existing interconnect layer fabrication process. The capacitor plates, dielectric layers, and contact structures are integrated into the same manufacturing sequence as the interconnect layers, eliminating the need for separate dedicated capacitor fabrication steps. This merging of processes reduces overall manufacturing complexity while maintaining decoupling capability.
Solution Approach 2:
The patent designs capacitor structures that can serve multiple functions within the integrated circuit. The same stacked plate structures provide both decoupling capacitance and can be integrated with power delivery networks and signal routing. This multi-functionality reduces the need for separate dedicated decoupling structures, thereby simplifying the overall device architecture and processing steps.
3Reliability
If capacitor density is increased to maintain decoupling in scaled devices, then decoupling effectiveness is maintained, but available space for other structures decreases
Solution Approach 1:
The patent addresses space constraints by moving capacitor structures into the vertical dimension through stacking. Multiple capacitor plates are arranged in layers along the depth direction, enabling high decoupling capacitance density without occupying additional lateral space. This allows other circuit structures to be placed in the previously required footprint area while maintaining decoupling effectiveness through the stacked configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively provides a higher quality power supply by decoupling AC noise from DC rails, while reducing the required space and complexity in integrated circuits.
Implementation Method 1
a capacitor within a dielectric region that is laterally adjacent to the device layer. The capacitor includes a plurality of first electrodes, each having a height in a first direction through an entire thickness of the dielectric region
Implementation Method 2
a capacitor within a dielectric region that is laterally adjacent to the device layer
Data Source
AI summary
Techniques are provided herein for forming one or more capacitors between backside power rails using backside contacts to the backside power rails. In one example, a capacitor includes a first plurality of plate-like electrodes that alternate with a second plurality of plate-like electrodes. Backside contacts are used to contact bottom surfaces of the first plurality of plate-like electrodes and bottom surfaces of the second plurality of plate-like electrodes. In another example, a capacitor includes a first plurality of plate-like electrodes and one or more second plate-like electrodes. A dielectric layer is present over the first plurality of plate-like electrodes. A conductive layer is present on the dielectric layer and also contacting at least one of the one or more second plate-like electrodes. Backside contacts are used to contact bottom surfaces of the first plurality of plate-like electrodes and bottom surfaces of the one or more second plate-like electrodes.