Backside-Mounted Die Packaging With Exposed Interconnects for High Frequencies
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional wirebond-based semiconductor device packaging methods face challenges at high frequencies due to parasitic effects and heat management issues, leading to variability in inductance and potential damage to the semiconductor dies.
Innovation Solution
The implementation of a flip-chip configuration with conductive bumps or pillars for electrical connections, along with a protective mold structure and thermally conductive substrates, allows for reduced parasitic effects and improved heat dissipation, eliminating the need for wirebonds and enhancing the effectiveness of matching circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wirebond-based connections are used for electrical connections in semiconductor device packages, then ease of manufacture is improved, but parasitic effects and inductance variability increase at high operating frequencies
Solution Approach 1:
The patent extracts and removes the wirebond interconnection layer from the device structure, transitioning to direct bond or flip-chip configurations where the die is bonded directly to the substrate without intermediate wire bonds. This elimination of the wirebond layer reduces parasitic inductance and improves high-frequency performance while maintaining manufacturing feasibility through established direct bonding processes.
Solution Approach 2:
The patent transitions from planar wirebond connections to vertical three-dimensional interconnections by implementing flip-chip or direct bond configurations. This dimensional change allows electrical connections to be made perpendicular to the substrate surface, significantly reducing the loop area and associated parasitic inductance while enabling better thermal management pathways.
2Ease of operation
If wirebond-based connections are used, then assembly process is simplified, but inductance variability increases leading to performance deterioration
Solution Approach 1:
The patent removes the wirebond interconnection element that causes inductance variability, replacing it with rigid direct bond or flip-chip connections. This extraction eliminates the mechanical flexibility and positioning tolerances that contribute to inductance variations, providing more consistent electrical performance across production batches.
Solution Approach 2:
The patent implements a universal bonding interface that simultaneously achieves electrical connection, mechanical support, and thermal management functions. This multi-functional direct bond or flip-chip configuration replaces the separate wirebond interconnection step, reducing assembly complexity while providing controlled and consistent electrical characteristics through precise bonding process control.
3Object-affected harmful factors
If conventional packaging is used, then device protection is achieved, but heat dissipation efficiency is reduced
Solution Approach 1:
The patent utilizes vertical three-dimensional heat dissipation pathways by implementing flip-chip or direct bond configurations with exposed die surfaces. This dimensional change allows heat to be extracted directly from the die through the substrate via thermal vias and heat sinks, creating efficient thermal management pathways that do not interfere with the protective packaging structure.
Solution Approach 2:
The patent segments the packaging structure to expose specific die surfaces while maintaining protection for other areas. This selective exposure allows direct thermal contact between the die and heat dissipation structures in critical regions, while the protective packaging remains intact for mechanical protection and environmental sealing in non-critical areas.
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a protective structure on at least one die on a substrate. The protective structure exposes one or more electrical contacts on a first surface of the at least one die. Respective terminals are formed on the one or more electrical contacts exposed by the protective structure. Related packages and fabrication methods are also discussed.