Back-Side Die Interconnect Structure Without Substrate Recessing
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing pin hole defects and improving yield and reliability in die structures due to the need for recessing semiconductor substrates, which can damage nitride liners during etching processes.
Innovation Solution
The implementation of a back-side interconnect structure with conductive vias formed on through-substrate vias (TSVs) without recessing the semiconductor substrate, using a nitride-oxide-nitride-oxide (NONO) gap-fill dielectric structure to avoid etching of nitride liners and reduce pin hole defects, and forming conductive features in dielectric layers to connect TSVs without substrate recessing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If semiconductor substrate is recessed to form vertical connections, then interconnect access is improved, but nitride liners are damaged and pin hole defects increase
Solution Approach 1:
The patent segments the interconnect formation process into two distinct parts: (1) forming TSVs through the semiconductor substrate to reach the interconnect, and (2) forming conductive vias through the dielectric layer to contact the TSVs. This segmentation eliminates the need for substrate recessing, as the conductive vias are formed separately in the dielectric layer after TSV formation, thereby preventing damage to nitride liners while maintaining interconnect access.
Solution Approach 2:
The patent transitions from a two-dimensional planar interconnect structure to a three-dimensional vertical structure by forming TSVs that extend through the substrate depth and conductive vias that extend through the dielectric layer depth. This dimensional change enables vertical connections without requiring substrate recessing, as the conductive vias are formed in the dielectric layer above the TSVs, accessing them from the top surface.
2Ease of manufacture
If nitride liners are etched during substrate recessing, then interconnect exposure is achieved, but liner damage occurs and yield decreases
Solution Approach 1:
The patent performs preliminary action by forming the TSVs through the semiconductor substrate before forming the conductive vias in the dielectric layer. The TSVs are pre-formed with nitride liners that protect the substrate during subsequent processing. The conductive vias are then formed to contact these pre-formed TSVs, eliminating the need for later substrate recessing that would damage the liners.
Solution Approach 2:
The patent introduces an intermediary dielectric layer between the semiconductor substrate and the final interconnect structure. Conductive vias are formed through this dielectric layer to contact the TSVs, serving as an intermediary structure that enables interconnect access without requiring direct etching of the substrate or damage to the nitride liners.
3Reliability
If through-substrate vias are formed to contact interconnect, then vertical connections are enabled, but substrate recessing is required which damages structure
Solution Approach 1:
The patent implements a nested structure where conductive vias are formed within the dielectric layer and nest around the TSVs. The TSVs are embedded in the substrate, and the conductive vias are formed in the dielectric layer to contact the TSVs, creating a nested arrangement that enables vertical connections without requiring substrate recessing or compromising structural integrity.
Data Source
AI summary
Die structures and methods of forming the same are described. In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die face-to-face bonded to the lower integrated circuit die, the first upper integrated circuit die including a first semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and with a top surface of the first through-substrate via; and an interconnect structure including a first dielectric layer and first conductive vias, the first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate, the first conductive vias extending through the first dielectric layer to contact the top surface of the first through-substrate via.