Backside Die-to-Package Interconnects for Pre-Bond Die Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for testing die functionality in integrated circuit (IC) packages are inadequate, especially for multi-die IC packages with fine pitch bonding layers, leading to increased manufacturing defects and costs due to the integration of non-functional subassemblies.
Innovation Solution
The implementation of backside die-to-package interconnects (DTP) and hybrid bonding (HB) techniques allows for testing die functionality in subassemblies by providing integrated interconnects to the backside of dies, enabling the separation of backside power grid customization and optimizing performance by matching high-performance base dies with top dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional testing methods are used for die functionality in multi-die IC packages, then manufacturing costs increase and assembly yields decrease, but implementing backside DTP interconnects adds device complexity and manufacturing process complexity
Solution Approach 1:
The patent segments the interconnect structure by providing separate backside DTP interconnects and frontside bonding interconnects. The backside interconnects enable testing functionality while the frontside interconnects handle signal transmission, dividing the package into distinct functional zones that can be optimized independently
Solution Approach 2:
The patent utilizes the backside dimension of the die for interconnect formation, moving testing functionality from the conventional frontside to the backside. This dimensional transition allows testing interconnects to coexist with signal interconnects without interfering with each other, thereby enabling testing capability without compromising signal performance
2Reliability
If backside DTP interconnects are implemented to enable testing, then functional testing before integration becomes possible, but the manufacturing process becomes more complex
Solution Approach 1:
The patent implements preliminary testing capability by forming backside DTP interconnects before die integration. This allows functional testing to be performed on individual dies or subassemblies prior to final package assembly, enabling defect detection and removal early in the manufacturing process
Solution Approach 2:
The backside DTP interconnect structure serves multiple functions: it provides testing capability for die functionality, enables power delivery to the die, and facilitates thermal management. This multi-functionality reduces the need for separate dedicated test structures
3Manufacturing precision
If fine pitch bonding layers are used in multi-die IC packages, then device performance improves, but testing die functionality becomes inadequate and manufacturing defects increase
Solution Approach 1:
The patent segments the interconnect function by dedicating frontside bonding interconnects to fine-pitch signal transmission and backside DTP interconnects to testing and power functions. This segmentation allows fine pitch bonding layers to maintain their high-performance signal transmission capability while separate backside interconnects provide robust testing functionality
Solution Approach 2:
The backside DTP interconnects act as an intermediary structure that enables testing functionality without interfering with the fine pitch frontside bonding layers. The intermediary testing structure on the backside provides the necessary test access points and power delivery while leaving the frontside signal paths intact
Data Source
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer, and including a first metallization stack at the first surface; a device layer on the first metallization stack; a second metallization stack on the device layer; and an interconnect on the first surface of the die electrically coupled to the first metallization stack; a conductive pillar in the first layer; and a second die, having a first surface and an opposing second surface, in a second layer on the first layer, wherein the first surface of the second die is coupled to the conductive pillar and to the second surface of the first die by a hybrid bonding region.