Backside Dielectric Stress Compensation for 3D IC TSVs

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The integration density of semiconductor components is limited by two-dimensional designs, leading to increased interconnections and circuit RC delay, and power consumption, which are addressed by exploring three-dimensional integrated circuits (3DIC) and stacked dies with through-silicon vias (TSVs).

Innovation Solution

A backside interconnect structure connected to TSVs is formed, with a passivation layer that applies stress to compensate for or enhance the stress caused by TSVs, thereby stabilizing the performance of PMOS and NMOS devices by adjusting the stress applied to the semiconductor substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If two-dimensional integrated circuit design is used, then manufacturing process is simpler, but integration density is limited and interconnection length increases

Engineering Contradiction:

Improveintegration densityVSAvoidinterconnection length

Core Design Contradiction:

Device complexityVSLength of moving object

Solution Approach 1:

The patent transitions from two-dimensional circuit design to three-dimensional stacked die architecture with through-silicon vias (TSVs), enabling vertical interconnections that significantly reduce interconnection length while increasing integration density. Multiple dies are stacked vertically and connected through TSVs, creating a 3D integrated circuit structure.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Device complexity

If three-dimensional integrated circuits with TSVs are used, then integration density increases and interconnection length decreases, but stress-induced performance drift occurs

Engineering Contradiction:

Improveintegration densityVSAvoiddevice performance stability

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent applies preliminary counter-stress through specifically engineered dielectric layers and stress compensation structures before device operation. These structures pre-compensate for the stress induced by TSVs, preventing performance drift before it occurs. The counter-stress is designed to balance the mechanical stress field in the semiconductor substrate.

Inventive Principle:

Principle #9Preliminary anti-action

Solution Approach 2:

The patent modifies material parameters and structural configurations of dielectric layers to control stress distribution. By changing the stress characteristics (tensile or compressive) of backside dielectric layers and stress compensation structures, the overall stress state in the substrate is adjusted to compensate for TSV-induced stress.

Inventive Principle:

Principle #35Parameter changes

3Reliability

If stress compensation structures are added, then device performance stability improves, but manufacturing process complexity increases

Engineering Contradiction:

Improvedevice performance stabilityVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent integrates stress compensation functions into existing manufacturing processes and structures. The backside dielectric layers and stress compensation structures serve multiple purposes: electrical isolation, mechanical stress control, and process integration. This multi-functionality reduces the need for separate dedicated stress compensation process steps.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The stress compensation or enhancement by the passivation layer reduces performance drift of PMOS and NMOS devices, achieving more uniform performance across the wafer and improving drive current, while maintaining or reducing overall stress levels.

Implementation Method 1

Methodology Applied

Scientific EffectStress compensation: Elasticity

Data Source

PatentUS8946084B2Controlling the device performance by forming a stressed backside dielectric layer

Publication Date: 2015.02.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.