Backside Dielectric Subfin Replacement for Lower Parasitic Leakage
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Solution Overview
Problem
As integrated circuits scale downward in size, parasitic effects such as parasitic capacitance and leakage current between densely packed semiconductor devices become significant, degrading transistor performance and switching speed.
Innovation Solution
Replace semiconductor subfins with dielectric materials, including a dielectric liner and fill, and optionally create airgaps to reduce parasitic capacitance and leakage current, by removing the substrate from the backside and etching away the semiconductor material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistors are packed more densely to reduce device size, then device spacing and memory cell size are reduced, but parasitic effects such as parasitic capacitance and leakage current increase and degrade device operation
Solution Approach 1:
The subfin semiconductor material is selectively removed from beneath the gate structure through backside etching, extracting the harmful parasitic elements while preserving the main fin structure and device functionality
Solution Approach 2:
Dielectric material is deposited only in the localized region beneath the gate structure where the subfin was removed, creating a spatially differentiated structure that reduces parasitic effects at the critical interface while maintaining device integrity elsewhere
2Object-generated harmful factors
If subfins are removed from the backside and replaced with dielectric material, then parasitic capacitance and leakage current are reduced, but device structure and fabrication process become more complex
Solution Approach 1:
Instead of modifying the subfin structure from the frontside, the patent approaches the problem from the backside of the device, removing the substrate and subfin material from beneath the gate and filling with dielectric, thereby simplifying the overall device architecture despite the additional fabrication steps
Solution Approach 2:
A dielectric material is introduced as an intermediary substance to replace the removed subfin semiconductor material, providing electrical isolation and reducing parasitic effects while maintaining structural integrity
Data Source
AI summary
Techniques are provided herein to form semiconductor devices that have their semiconductor subfins removed and replaced with one or more dielectric materials. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the semiconductor material includes a subfin adjacent to a dielectric layer that acts as shallow trench isolation (STI) between semiconductor devices. A backside process may be performed to remove the bulk substrate and expose a bottom surface of the subfin. The subfin may then be removed from the backside to form backside recesses. A dielectric liner may be formed within the backside recesses and a dielectric fill may be formed within a remaining volume of the backside recesses. Replacing the subfins with dielectric materials may lower parasitic capacitance between the subfins and the gate electrodes as well as reduce parasitic current between adjacent source or drain regions.