Backside Doped Semiconductor Structure for Stable Scaled Transistors
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Solution Overview
Problem
The scaling down of transistors in memory devices is limited by high-temperature processes, making it difficult to maintain desired characteristics and apply low-temperature processes effectively, which affects the performance and reliability of semiconductor devices.
Innovation Solution
A semiconductor device design that includes a substrate with a device isolation layer, a gate electrode, and a wiring structure, where a protective insulating layer covers the wiring structure, and dopant regions are formed by implanting dopants through the substrate's surface, with different concentrations to enhance performance and reliability, particularly by preventing performance changes during high-temperature processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If high-temperature process is applied to semiconductor devices, then transistor scaling down is enabled, but transistor performance changes and reliability deteriorates
Solution Approach 1:
The device isolation layer is formed to extend through the substrate before transistor fabrication, establishing a baseline structure that prevents performance degradation during subsequent high-temperature processes. This preliminary structural preparation ensures transistor characteristics remain stable throughout manufacturing.
Solution Approach 2:
The device isolation layer acts as an intermediary structure between the substrate and transistor components, providing thermal and structural isolation that protects transistors from harmful high-temperature effects while allowing the process to continue.
2Ease of manufacture
If high-temperature process is applied to semiconductor devices, then manufacturing is enabled, but transistor characteristics change
Solution Approach 1:
The device isolation layer is formed to extend through the substrate before transistor fabrication, establishing a baseline structure that prevents performance degradation during subsequent high-temperature processes. This preliminary structural preparation ensures transistor characteristics remain stable throughout manufacturing.
Solution Approach 2:
The device isolation layer provides localized protection to specific transistor regions, allowing different parts of the device to experience different thermal environments. This localized quality control maintains transistor characteristics in protected regions while allowing manufacturing to proceed.
3Reliability
If low-temperature process is applied to semiconductor devices, then transistor performance is maintained, but desired memory device characteristics cannot be obtained
Solution Approach 1:
The device isolation layer provides localized protection to specific transistor regions, allowing different parts of the device to experience different thermal environments. This localized quality control maintains transistor characteristics in protected regions while allowing manufacturing to proceed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design increases the reliability and performance of semiconductor devices by maintaining transistor characteristics and allowing for the use of low-temperature processes, thereby overcoming the limitations of high-temperature scaling issues.
Implementation Method 1
The target doped region and the path doped region are formed by implanting the dopant through the second surface of the substrate
Implementation Method 2
The substrate is thinned by grinding the second surface of the substrate to expose the second surface of the device isolation layer
Data Source
AI summary
A semiconductor device includes a substrate including first and second surfaces opposing each other. A device isolation layer extends through the substrate and defines an active region in the substrate. A gate electrode is on the first surface of the substrate. A wiring structure electrically connects the gate electrode and the active region. The active region includes a target doped region between the device isolation layer and the gate electrode and including a dopant having a first concentration. A path doped region is between the device isolation layer and the gate electrode and extends from the second surface of the substrate to the target doped region. The path doped region includes a dopant having a second concentration less than the first concentration. The target doped region and the path doped region are formed by implanting the dopant through the second surface of the substrate.