Backside Drain Contact Layout for Dense Semiconductor Transistors
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Solution Overview
Problem
The increasing complexity and density of semiconductor integrated circuits (ICs) lead to higher power dissipation and reduced processing efficiency due to smaller metal lines, which worsen RC delay and IR drop, necessitating improved metal line routing methods to enhance functional density and performance.
Innovation Solution
The method involves transferring part of the metal layers to the wafer back-side to reduce routing loading and improve circuit density, by moving a common rectangular drain contact from the front-side to the back-side and electrically connecting it to front-side metal layers, thereby reducing lateral overlapping area and improving capacitance between the contact and gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If common drain contacts are placed on the front-side of the wafer, then the manufacturing process is simpler, but the lateral overlap with gate structures increases causing higher capacitance and reduced functional density
Solution Approach 1:
The patent moves drain contacts from the front-side (2D plane) to the back-side of the wafer, utilizing the third dimension (depth/vertical stacking) to resolve the lateral overlap issue. This dimensional transition allows drain contacts to be positioned beneath gate structures without lateral interference, reducing capacitance while maintaining manufacturing feasibility through back-side processing techniques
2Device complexity
If metal lines are made denser to increase functional density, then more circuits can be integrated, but power dissipation and resistance increase reducing performance
Solution Approach 1:
By relocating drain contacts to the back-side and implementing vertical interconnect structures, the patent reduces the lateral metal line routing distance and cross-section area. This dimensional reorganization decreases resistive losses and power dissipation in metal interconnects while enabling higher functional density through more efficient space utilization
3Manufacturing precision
If the lateral overlap between drain contacts and gate structures is increased, then the manufacturing alignment is more tolerant, but the capacitance increases reducing operational speed
Solution Approach 1:
The patent transitions drain contacts from a lateral positioning scheme to a vertical stacking scheme where drain contacts on the back-side are aligned with gate structures through vertical interconnects rather than lateral overlap. This eliminates the trade-off between alignment tolerance and capacitance by decoupling the positioning dimensions, allowing precise vertical alignment while minimizing capacitive coupling
Data Source
AI summary
A method includes forming a first transistor comprising a first channel region, a first gate structure surrounding the first channel region, and first source/drain regions on opposite sides of the first gate structure; forming a second transistor comprising a second channel region, a second gate structure surrounding the second channel region, and second source/drain regions on opposite sides of the second gate structure; forming a front-side contact on a top end of a first one of the first source/drain regions of the first transistor; forming a first back-side contact extending from a bottom end of the first one of the first source/drain regions of the first transistor to a bottom end of a first one of the second source/drain regions of the second transistor.