Backside Drain Resistance Layout for MOSFET ESD Immunity
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Solution Overview
Problem
Existing semiconductor devices face challenges in providing effective electrostatic discharge (ESD) immunity, particularly in advanced MOSFET and CMOS devices, due to damage from high-energy ESD pulses that can break down the gate oxide layer, leading to permanent circuit failure.
Innovation Solution
Incorporating a through substrate resistive component connected in series with the drain terminal of transistors, which provides additional resistance to shield the drain from direct ESD stress, utilizing a BEOL and B-BEOL fabrication process to integrate a resistive component into the semiconductor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large space is added between the drain metal contact and the gate edge to add resistance in series with the drain, then ESD immunity is improved, but epitaxy quality deteriorates leading to ESD performance degradation
Solution Approach 1:
The patent transitions from a planar layout approach to a three-dimensional vertical structure by forming a drain extension region that extends downward from the drain contact into the semiconductor substrate. This vertical dimension allows the drain extension to be in series with the drain without requiring lateral spacing, thus maintaining epitaxy quality while providing the necessary resistance for ESD immunity.
Solution Approach 2:
The drain region is segmented into a main drain contact area and a separate drain extension region that extends vertically into the substrate. This segmentation allows the drain extension to function as a separate resistive element in series with the drain, providing ESD protection while maintaining the integrity of the main drain structure and epitaxy quality.
2Productivity
If advanced MOSFET and CMOS devices are fabricated with higher integration, then circuit functionality is improved, but susceptibility to ESD damage increases due to smaller internal transistors and tighter spacing
Solution Approach 1:
By utilizing the vertical dimension through drain extensions that extend into the substrate, the patent adds ESD protection capability without consuming lateral space. This allows highly integrated circuits with tight spacing to maintain ESD immunity through the vertically-oriented drain extension structure.
Solution Approach 2:
The drain extension region acts as an intermediary element between the drain contact and the channel region. It provides a series resistance that limits ESD current while maintaining normal device operation, thus protecting the tightly-spaced internal transistors in highly integrated circuits from ESD damage.
3Loss of energy
If ESD current flows through the drain to substrate or gate, then the ESD pulse is dissipated, but permanent damage occurs to the gate oxide layer
Solution Approach 1:
The drain extension region is specifically designed with different properties than the main drain - it extends into the substrate and provides a controlled resistive path. This local modification creates a preferential current path through the drain extension into the substrate, away from the gate oxide, thus dissipating ESD energy while protecting the gate oxide from damage.
Solution Approach 2:
The patent converts the potentially harmful direct ESD current path through the gate oxide into a beneficial protected path by providing the drain extension as an alternative route. The drain extension's series resistance limits the current, and its vertical extension into the substrate provides a safe discharge path that converts the harmful ESD pulse into controlled energy dissipation away from sensitive structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances ESD immunity by allowing the drain to tolerate higher ESD voltages and large hot carrier injections, reducing the risk of gate oxide damage and improving epitaxy control during deep-submicron fabrication.
Implementation Method 1
Incorporating a through substrate resistive component connected in series with the drain terminal of transistors, which provides additional resistance to shield the drain from direct ESD stress
Data Source
AI summary
An apparatus for providing electrostatic discharge (ESD) immunity and a method for fabricating the same are disclosed herein. The apparatus comprises a field effect transistor (FET) formed on a semiconductor substrate in a front-end-of-line (FEOL) layer during an FEOL process, a metal interconnect layer formed on top of the FEOL layer during a back-end-of-line (BEOL) process, wherein the metal interconnect layer comprises a plurality interconnects configured to interconnect the FET to a plurality of components formed on the semiconductor substrate, a power delivery network (PDN) formed under the semiconductor substrate in a backside layer during a backside back-end-of-line (B-BEOL) process, and a through substrate resistive component formed between the FEOL and B-BEOL layers, wherein a first contact of the through substrate resistive component is connected to a drain terminal of the FET and second contact is connected, through the PDN, to a power supply rail.