Backside DRAM and Power Delivery for Dense Nanowire IC Layouts
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Solution Overview
Problem
The scaling of multi-gate and nanowire transistors in integrated circuits poses challenges in maintaining mobility and short channel control, particularly due to constraints on lithographic processes, and there is a need for efficient power delivery in high bandwidth computing applications.
Innovation Solution
The integration of dynamic random access memory (DRAM) on the backside of a wafer or substrate with power delivery, allowing for reduced power network resistance and improved performance by eliminating the need for wide metal wires on the front side, enabling compact cell architectures and efficient signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate and nanowire transistors are scaled down to increase device density, then the number of memory or logic devices on a chip increases, but maintaining mobility improvement and short channel control becomes increasingly difficult
Solution Approach 1:
The patent implements backside DRAM architecture where memory cells are formed on the backside of the substrate, utilizing the third dimension (vertical stacking) to separate logic and memory functions. This dimensional separation allows independent optimization of logic transistors for high density and memory structures for high bandwidth, resolving the conflict between scaling density and maintaining control.
2Productivity
If the smallest dimension of features is reduced to increase device density, then more devices can be fabricated in a given region, but the spacing between features becomes constrained by lithographic process limits
Solution Approach 1:
By moving memory formation to the backside of the substrate, the patent utilizes vertical stacking to achieve high device density without further reducing lateral feature dimensions. This eliminates the need to push lithographic limits and maintains manufacturable feature spacing while still achieving increased density through the third dimension.
Solution Approach 2:
The patent segments the substrate into frontside logic region and backside memory region, allowing each to be optimized independently for its specific function. The logic region can use advanced lithography for dense transistor gating, while the memory region on the backside can use larger, more manufacturable feature sizes.
3Power
If wide metal wires are used on the front side to deliver power, then power delivery capability improves, but the area available for logic devices and signal routing is reduced
Solution Approach 1:
The patent moves power delivery for memory operations to the backside of the substrate, where dedicated power and ground lines can be formed without consuming frontside logic area. This spatial separation in the third dimension allows the front side to be fully utilized for high-density logic while the backside handles power delivery and memory functions.
Data Source
AI summary
Structures having memory with backside DRAM and power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a plurality of dynamic random access memory (DRAM) devices.