Backside eFuse Bit Cell Layout for Lower IR Drop
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Solution Overview
Problem
Integrated circuits with one-time-programmable (OTP) memory elements, such as electrical fuses (eFuses), face challenges in determining the status of the fuse elements efficiently and securely, leading to potential reliability issues and data security concerns due to high IR drops and insecure storage of information.
Innovation Solution
The design of an efuse bit cell with a fuse element at the backside of the substrate, featuring a transistor with source and drain terminals connected to a power node and an efuse node, and mesh structures in both front-side and backside metal layers, reduces IR drops and enhances security by increasing line widths of conducting lines, thereby improving reliability and security of stored information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional front-side fuse element design is used, then device complexity is reduced, but IR drops increase and reliability deteriorates
Solution Approach 1:
The fuse element is moved from the front side to the back side of the substrate, utilizing the third dimension (depth/layer) to resolve the contradiction. This dimensional transition allows the fuse element to access broader interconnect resources on the back side, reducing IR drops while maintaining integration within the existing substrate structure.
Solution Approach 2:
The substrate is divided into front-side and back-side regions with distinct functional assignments. The front side contains sense circuits and control logic, while the back side houses the fuse element and associated interconnects. This segmentation allows each side to be optimized independently, improving reliability without excessive complexity.
2Reliability
If narrow stripe link is used, then device complexity is reduced, but IR drops increase leading to reliability issues
Solution Approach 1:
By relocating the fuse element to the back side of the substrate, the design accesses additional interconnect layers and wider conducting lines that are available on the back side. This dimensional change directly reduces IR drops by providing lower resistance paths for current flow, thereby improving reliability without increasing energy loss.
3Reliability
If traditional storage mechanism is used, then ease of manufacture is improved, but security of stored information deteriorates
Solution Approach 1:
Storing fuse information on the back side of the substrate provides physical security advantages, as the back side is less accessible and more difficult to tamper with compared to the front side. This dimensional relocation enhances security while maintaining compatibility with existing manufacturing processes through standard back-side interconnect formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed efuse bit cell design reduces IR drops, enhancing the reliability of the integrated circuit and securing stored information by minimizing IR drops and providing a more secure storage mechanism compared to traditional implementations.
Implementation Method 1
The IR drop of the power node or the efuse node is reduced, when the line widths of the conducting lines in the corresponding mesh structure are increased
Data Source
AI summary
An integrated circuit includes a front-side horizontal conducting line in a first metal layer, a front-side vertical conducting line in a second metal layer, a front-side fuse element, and a backside conducting line. The front-side horizontal conducting line is directly connected to the drain terminal-conductor of a transistor through a front-side terminal via-connector. The front-side vertical conducting line is directly connected to the front-side horizontal conducting line through a front-side metal-to-metal via-connector. The front-side fuse element having a first fuse terminal conductively connected to the front-side vertical conducting line. The backside conducting line is directly connected to the source terminal-conductor of the transistor through a backside terminal via-connector.