Backside Epitaxial Contacts for Low-Resistance FET Source/Drain

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Solution Overview

Problem

The challenge in semiconductor manufacturing is reducing contact resistance in field effect transistors (FETs) as they scale down, particularly due to high Schottky barrier heights between metal silicide layers and source/drain regions, which affects performance and power consumption, and existing methods struggle to achieve low contact resistances for both n-type and p-type FETs without degrading device performance.

Innovation Solution

The implementation of epitaxial contact structures with a larger second portion and active dopant concentrations higher than 1×10^21 cm^-3, and the use of different metal silicide layers for n-type and p-type FETs to reduce Schottky barrier heights, increasing contact area and reducing contact resistance by 30% to 70%.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If metal silicide layers are used for contact structures, then manufacturing is simplified, but Schottky barrier heights increase causing high contact resistance

Engineering Contradiction:
Improvecontact structure fabricationVSAvoidcontact resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the physical and chemical parameters of the contact structure by introducing epitaxial growth processes, modifying dopant concentrations (>1×10^21 cm^-3), and creating multi-layer metal silicide structures with different thicknesses and compositions. These parameter changes reduce Schottky barrier heights and contact resistance while maintaining manufacturability through controlled epitaxial processes.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite contact structures consisting of multiple metal silicide layers (e.g., CoSi2, NiSi, TiSi2) with different properties, combined with epitaxially grown semiconductor layers. This composite approach allows optimization of each layer's function: some layers provide low resistance, others provide good adhesion or barrier properties, collectively reducing overall contact resistance while maintaining ease of manufacture.

Inventive Principle:
Principle #40Composite materials

2Reliability

If contact area is increased to reduce contact resistance, then device area increases, but contact resistance decreases

Engineering Contradiction:
Improvecontact resistanceVSAvoiddevice area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from two-dimensional planar contacts to three-dimensional epitaxial contact structures with vertical extension. By growing contacts vertically into the substrate and creating multi-layer structures, the contact area is increased in the vertical dimension without proportionally increasing the horizontal device footprint, thus reducing contact resistance while minimizing area penalty.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested contact structures where smaller contact regions are positioned within or adjacent to larger contact regions, and multiple metal silicide layers are nested within each other. This nesting allows efficient use of space while maximizing the effective contact area through vertical stacking and strategic positioning, reducing contact resistance without excessive area increase.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces contact resistance in backside contact structures by increasing the contact area and optimizing dopant concentrations, improving device performance and power delivery while maintaining low resistance for both n-type and p-type FETs.

Implementation Method 1

forming an epitaxial contact structure on the source/drain (S/D) region in the opening

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

active dopant concentrations higher than 1×10^21 cm^-3

Methodology Applied
Scientific EffectDoping: Dopants

Data Source

PatentUS20240371952A1Backside contact structures for semiconductor devices
Publication Date: 2024.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240371952A1 patent drawing
  • US20240371952A1 patent drawing
  • US20240371952A1 patent drawing

AI summary

The present disclosure describes a method to form a semiconductor device with backside contact structures. The method includes forming a semiconductor device on a first side of a substrate. The semiconductor device includes a source/drain (S/D) region. The method further includes etching a portion of the S/D region on a second side of the substrate to form an opening and forming an epitaxial contact structure on the S/D region in the opening. The second side is opposite to the first side. The epitaxial contact structure includes a first portion in contact with the S/D region in the opening and a second portion on the first portion. A width of the second portion is larger than the first portion.