Backside Power Rail Contacts Under Epitaxy for Lower Voltage Drop
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Solution Overview
Problem
As semiconductor technology advances into sub-10 nanometer process nodes, existing methods for forming power rails on the backside of integrated circuits (ICs) fail to adequately reduce resistance and coupling capacitance, leading to increased voltage drop and power consumption.
Innovation Solution
The formation of sacrificial contact vias on the backside of the wafer before channel structures are formed, which are later replaced by conductive vias, allowing for a larger contact area between source/drain epitaxial features and power rails, thereby reducing contact resistance and improving device performance, and the integration of backside power rails to increase metal tracks and gate density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power rails are formed on the backside of the IC, then voltage drop is reduced, but contact resistance increases due to limited contact area
Solution Approach 1:
Sacrificial contact vias are formed in advance during the fabrication process, before the IC is completed and flipped. These sacrificial features are subsequently replaced with conductive material to create the final contact vias. This preliminary action enables the formation of adequate contact area between power rails and source/drain regions while maintaining the backside power rail configuration.
Solution Approach 2:
Sacrificial contact vias serve as intermediary structures during fabrication. These temporary features are formed, then replaced with conductive material to create the actual electrical contacts. The sacrificial vias mediate the transition from fabrication-friendly processes to final functional structures, enabling both adequate contact area and low contact resistance.
2Ease of manufacture
If conventional power rail formation methods are used, then manufacturing is simpler, but resistance and coupling capacitance are not adequately reduced
Solution Approach 1:
The power rail structure transitions from a planar configuration to a three-dimensional structure by extending power rails to the backside of the IC. This dimensional change creates additional metal tracks and reduces coupling capacitance between adjacent power rails, thereby reducing power consumption while maintaining compatibility with conventional fabrication processes.
Solution Approach 2:
The power delivery network is segmented into frontside and backside components. Power rails are distributed across both surfaces of the IC, with conductive vias providing vertical interconnections. This segmentation reduces the length of current paths and decreases overall resistance, leading to lower power consumption.
3Reliability
If more metal tracks are added to reduce resistance, then device complexity increases
Solution Approach 1:
Instead of adding more metal tracks on the frontside, the power rail structure is inverted by extending rails to the backside of the IC. This inversion utilizes the unused backside area to create additional current paths, effectively reducing resistance without increasing frontside complexity or requiring additional processing steps.
Data Source
AI summary
A semiconductor structure includes channel structures vertically stacked, a gate structure engaging the channel structures, an epitaxial feature abutting the channel structures, a backside interconnect layer disposed under the epitaxial feature, and a backside metal contact disposed directly under the epitaxial feature and electrically coupling the epitaxial feature to the backside interconnect layer. In a cross-sectional view of the semiconductor structure along a lengthwise direction of the channel structures, the backside metal contact extends to a position directly under the channel structures.