Backside Epitaxy Layout for Lower FET Contact Resistance
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Solution Overview
Problem
Current semiconductor technologies face challenges in scaling beyond 5 nm due to increasing process complexities and costs, particularly in reducing contact resistance and current crowding in field effect transistors.
Innovation Solution
The implementation of a highly doped epitaxy with a polygon shape on the backside of semiconductor structures, which is in electrical contact with the source/drain epitaxy and a metal backside contact, increasing the contact area and reducing contact resistance and current crowding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional scaling approaches are used to reduce transistor size, then device density increases, but contact resistance and current crowding worsen
Solution Approach 1:
The patent introduces a vertical dimension by forming a backside epitaxial structure that extends from the rear surface of the substrate toward the front side. This three-dimensional approach allows current to flow through multiple paths (front contact, through-substrate, and backside contact), effectively reducing current crowding and contact resistance while maintaining high device density on the front surface.
Solution Approach 2:
The backside epitaxial structure is nested within the substrate thickness, with the epitaxial layer grown from the backside surface and extending partially or fully through the substrate. This nested configuration provides additional conductive pathways without increasing the footprint area, thereby reducing contact resistance while maintaining compact device geometry.
2Productivity
If transistor dimensions are reduced for scaling, then more devices fit on chip, but process complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the current flow path into multiple independent regions: front contact regions, substrate regions, and backside contact regions. The backside epitaxial structure is formed as a separate, dedicated component that handles current distribution independently from the front-side transistor fabrication, simplifying the overall process by dividing complex functions into manageable segments.
Solution Approach 2:
The backside epitaxial structure acts as an intermediary element between the substrate and the backside contacts. It provides a controlled, highly doped region that facilitates current flow and reduces resistance without requiring direct modification of the front-side transistor structures, thereby simplifying the fabrication process while achieving the desired electrical performance.
3Ease of manufacture
If conventional contact structures are used, then fabrication is simpler, but current crowding and resistance increase at smaller nodes
Solution Approach 1:
Instead of attempting to reduce contact resistance through planar geometry optimization on the front surface, the patent transitions to a three-dimensional solution by adding a backside epitaxial structure. This vertical extension creates additional current flow paths through the substrate thickness, effectively distributing current and reducing crowding without complicating the front-side fabrication process.
Solution Approach 2:
The patent changes the electrical parameters of the substrate region by forming a highly doped epitaxial layer on the backside. This parameter change (increased doping concentration) significantly reduces the resistivity of the epitaxial region, thereby reducing contact resistance and current crowding effects while maintaining compatibility with standard fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the operation of semiconductor devices by reducing contact resistance and current crowding, thereby improving performance and addressing the scaling challenges in advanced technology nodes.
Implementation Method 1
generating a backside epitaxy by performing backside epitaxial growth of a highly-doped epitaxy on the S/D epitaxy
Data Source
AI summary
Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a field effect transistor (FET). The FET includes a source/drain (S/D) epitaxy and a metal gate. Additionally, the semiconductor structure includes a backside epitaxy in electrical contact with the S/D epitaxy. Further, the backside epitaxy includes a highly doped epitaxy. Additionally, the semiconductor structure includes a backside contact in electrical contact with the backside epitaxy. Further, the semiconductor structure includes a backside power distribution network in electrical contact with the backside contact.