Backside ESD Protection Circuit for Low-Capacitance High-Speed I/O

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Solution Overview

Problem

Existing electrostatic discharge (ESD) protection circuits in integrated circuits face challenges in minimizing intrinsic resistance to shunt ESD to ground while maintaining low parasitic capacitance, especially in high-frequency applications like USB 3.1/4 and HDMI interfaces, which can affect signal integrity.

Innovation Solution

The method involves forming ESD protection devices on the front side of a semiconductor substrate, creating contact pads, thinning the backside, and forming metal connections during backside processing to reduce capacitance and enhance signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the ESD protection circuit uses larger overlap area between metal connection and device structure, then the intrinsic resistance decreases providing better ESD protection, but the parasitic capacitance increases affecting signal integrity

Engineering Contradiction:
ImproveESD protection effectivenessVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent transitions from planar overlap connection to three-dimensional vertical connection by forming the metal connection below the device structure through backside thinning and metal deposition. This spatial reconfiguration reduces the overlapping area between metal connection and device structure, thereby reducing parasitic capacitance while maintaining effective ESD protection through the vertical conduction path.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Instead of forming the metal connection above and overlapping the device structure (conventional approach), the patent inverts the approach by forming the metal connection below the device structure on the backside of the substrate. This inversion reduces capacitance while still providing low-resistance ESD shunt path through the substrate.

Inventive Principle:
Principle #13The other way round (Inversion)

2Object-affected harmful factors

If the ESD protection circuit minimizes parasitic capacitance for high-frequency applications, then signal integrity is maintained, but the intrinsic resistance may increase reducing ESD protection effectiveness

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidESD protection effectiveness
Core Design Contradiction:
Object-affected harmful factorsVSReliability

Solution Approach 1:

The patent achieves low parasitic capacitance through reduced planar overlap by forming the metal connection in the vertical dimension below the device structure. Simultaneously, it maintains low intrinsic resistance through the direct vertical conduction path through the thinned substrate, resolving the trade-off between capacitance minimization and resistance reduction.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the geometric parameters of the metal connection by reducing its overlap area with the device structure and positioning it in a different spatial dimension (below rather than above). This parameter change reduces parasitic capacitance while the direct vertical path maintains low intrinsic resistance for effective ESD protection.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If conventional front-side processing is used for forming metal connections, then manufacturing process is simpler, but parasitic capacitance increases affecting high-frequency performance

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidparasitic capacitance
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent moves the metal connection formation from the front side (two-dimensional planar processing) to the back side (three-dimensional vertical processing). This dimensional change reduces the overlap area and parasitic capacitance while the added backside thinning and metal deposition steps manage the increased manufacturing complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent segments the manufacturing process into distinct front-side processing (device structure formation) and back-side processing (metal connection formation). This segmentation allows independent optimization of each stage, enabling reduced parasitic capacitance through backside connection while managing process complexity through systematic division of steps.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12463115B2Electrostatic discharge protection circuit
Publication Date: 2025.11.04 INFINEON TECHNOLOGIES AG
  • US12463115B2 patent drawing
  • US12463115B2 patent drawing
  • US12463115B2 patent drawing

AI summary

An electrostatic discharge protection circuit includes: a first electrostatic discharge protection device structure; a first contact pad above the first electrostatic discharge protection device structure in a cross-sectional view; and below the first electrostatic discharge protection device structure in the cross-sectional view, a metal connection coupling the first electrostatic discharge protection device structure to a second contact pad remote from the first contact pad, wherein the metal connection in the cross-sectional view only partially overlaps the first electrostatic discharge protection device structure.